Fatsie on double_addfile
Fatsie on dev
class Memory: add reset_less pa… Pin: Support providing reset be… (compare)
Fatsie on reset_enum
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_value
Fatsie on reset_enum
Signal: allow to use integral E… (compare)
Fatsie on reset_value
back.rtlil: extend shorter oper… vendor.xilinx_*: Set IOB attrib… hdl.ir: for instance ports, pri… and 9 more (compare)
Fatsie on memory_resetless
test: add tests for build.plat.… build.plat: in Platform.add_fil… class Memory: add reset_less pa… (compare)
Fatsie on double_addfile
Platform.add_file(): Allow to a… (compare)
Fatsie on memory_defsimulate
class Memory: allow to set defa… (compare)
Fatsie on record_name
Fatsie on record_name
Record: force name to be given … (compare)
pmos
and nmos
with varying drive strengths, because that is where much of my work is done. If it could also optimize to infer AOI and OAI where appropriate, that would be great. Mixed synthesis is not important to me because any VHDL IP I convert into (System)Verilog.
alpha
release in July 2019. For this year: The OpenROAD v1.0 tool, to be released in July 2020, will be capable of push-button, DRC-clean RTL-to-GDS layout generation in a commercial FinFET process node.
The FinFET process node they are targeting is 14/12 nm: a lot finer than what I need. Thanks again for the pointer, @Fatsie_gitlab and @Zeptobars_twitter https://vlsicad.ucsd.edu/NEWS19/OpenROAD%20RTL-to-GDS%20v1.0%20Expectations.pdf