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  • Apr 20 21:56

    MikePopoloski on master

    Add a specialized diagnostic fo… Add parsing support for checkers Fix parsing of let declarations (compare)

  • Apr 17 06:41
    jankcorn commented #392
  • Apr 17 06:41
    jankcorn commented #392
  • Apr 17 02:13
    MikePopoloski closed #392
  • Apr 17 02:13
    MikePopoloski closed #392
  • Apr 17 02:13
    MikePopoloski commented #392
  • Apr 17 02:13
    MikePopoloski commented #392
  • Apr 17 01:47

    MikePopoloski on master

    Fix to allow immediate deferred… Fix diagnostic printing of type… Fix type compatibility checking… (compare)

  • Apr 16 21:05
    MikePopoloski commented #392
  • Apr 16 21:05
    MikePopoloski commented #392
  • Apr 15 21:40
    jankcorn edited #392
  • Apr 15 21:40
    jankcorn edited #392
  • Apr 15 18:26
    codecov[bot] commented #392
  • Apr 15 18:26
    codecov[bot] commented #392
  • Apr 15 17:28
    jankcorn opened #392
  • Apr 15 17:28
    jankcorn opened #392
  • Apr 11 19:45

    MikePopoloski on master

    Fix clang warnings (compare)

  • Apr 11 17:36

    MikePopoloski on master

    Support first_match operator, c… Support weak, strong, and unary… Support abort and conditional p… and 2 more (compare)

  • Apr 10 21:30

    MikePopoloski on master

    Support binary sequence and pro… Fix parsing of parenthesized se… (compare)

  • Apr 09 23:16

    MikePopoloski on master

    Fix clang build (compare)

Michael Popoloski
@MikePopoloski
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_sync_synth.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1r1w_synth.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_bit_synth.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_mask_write_byte_synth.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_1rw_sync_synth.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync.v
black-parrot/external/basejump_stl/bsg_mem/bsg_mem_2r1w_sync_synth.v
black-parrot/external/basejump_stl/bsg_misc/bsg_adder_cin.v
black-parrot/external/basejump_stl/bsg_misc/bsg_adder_one_hot.v
black-parrot/external/basejump_stl/bsg_misc/bsg_adder_ripple_carry.v
black-parrot/external/basejump_stl/bsg_misc/bsg_arb_fixed.v
black-parrot/external/basejump_stl/bsg_misc/bsg_array_concentrate_static.v
black-parrot/external/basejump_stl/bsg_misc/bsg_buf.v
black-parrot/external/basejump_stl/bsg_misc/bsg_buf_ctrl.v
black-parrot/external/basejump_stl/bsg_misc/bsg_circular_ptr.v
black-parrot/external/basejump_stl/bsg_misc/bsg_concentrate_static.v
black-parrot/external/basejump_stl/bsg_misc/bsg_counter_clear_up.v
black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_down.v
black-parrot/external/basejump_stl/bsg_misc/bsg_counter_set_en.v
black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down.v
black-parrot/external/basejump_stl/bsg_misc/bsg_counter_up_down_variable.v
black-parrot/external/basejump_stl/bsg_misc/bsg_crossbar_o_by_i.v
black-parrot/external/basejump_stl/bsg_misc/bsg_cycle_counter.v
black-parrot/external/basejump_stl/bsg_misc/bsg_decode.v
black-parrot/external/basejump_stl/bsg_misc/bsg_decode_with_v.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_en_bypass.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en_bypass.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_chain.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_en.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_en.v
black-parrot/external/basejump_stl/bsg_misc/bsg_dff_reset_set_clear.v
black-parrot/external/basejump_stl/bsg_misc/bsg_edge_detect.v
black-parrot/external/basejump_stl/bsg_misc/bsg_encode_one_hot.v
black-parrot/external/basejump_stl/bsg_misc/bsg_expand_bitmask.v
black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank.v
black-parrot/external/basejump_stl/bsg_misc/bsg_hash_bank_reverse.v
black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative.v
black-parrot/external/basejump_stl/bsg_misc/bsg_idiv_iterative_controller.v
black-parrot/external/basejump_stl/bsg_misc/bsg_lfsr.v
black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_decode.v
black-parrot/external/basejump_stl/bsg_misc/bsg_lru_pseudo_tree_encode.v
black-parrot/external/basejump_stl/bsg_misc/bsg_mux.v
black-parrot/external/basejump_stl/bsg_misc/bsg_mux_bitwise.v
black-parrot/external/basejump_stl/bsg_misc/bsg_mux_butterfly.v
black-parrot/external/basejump_stl/bsg_misc/bsg_mux_one_hot.v
black-parrot/external/basejump_stl/bsg_misc/bsg_mux_segmented.v
black-parrot/external/basejump_stl/bsg_misc/bsg_muxi2_gatestack.v
black-parrot/external/basejump_stl/bsg_misc/bsg_nor2.v
black-parrot/external/basejump_stl/bsg_misc/bsg_nor3.v
black-parrot/external/basejump_stl/bsg_misc/bsg_nand.v
black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode.v
black-parrot/external/basejump_stl/bsg_misc/bsg_priority_encode_one_hot_out.v
black-parrot/external/basejump_stl/bsg_misc/bsg_reduce.v
black-parrot/external/basejump_stl/bsg_misc/bsg_reduce_segmented.v
black-parrot/external/basejump_stl/bsg_misc/bsg_rotate_left.v
black-parrot/external/basejump_stl/bsg_misc/bsg_rotate_right.v
black-parrot/external/basejump_stl/bsg_misc/bsg_round_robin_arb.v
black-parrot/external/basejump_stl/bsg_misc/bsg_scan.v
black-parrot/external/basejump_stl/bsg_misc/bsg_strobe.v
black-parrot/external/basejump_stl/bsg_misc/bsg_swap.v
black-parrot/external/basejump_stl/bsg_misc/bsg_thermometer_count.v
black-parrot/external/basejump_stl/bsg_misc/bsg_transpose.v
black-parrot/external/basejump_stl/bsg_misc/bsg_unconcentrate_static.v
black-parrot/external/basejump_stl/bsg_misc/bsg_xnor.v
black-parrot/external/basejump_stl/bsg_noc/bsg_mesh_stitch.v
black-parrot/external/basejump_stl/bsg_noc/bsg_noc_repeater_node.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_in.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_concentrator_out.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_in.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_adapter_out.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_decoder_dor.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_input_control.v
black-parrot/external/basejump_stl/bsg_noc/bsg_wormhole_router_output_control.v
black-parrot/bp_common/src/v/bsg_fifo_1r1w_rolly.v
black-parrot/bp_common/src/v/bp_pma.v
black-parrot/bp_common/src/v/bp_tlb.v
black-parrot/bp_be/src/v/bp_be_top.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_bypass.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_calculator_top.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_instr_decoder.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_int_alu.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_fp.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_int.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_ctrl.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_long.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mem.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_pipe_mul.v
black-parrot/bp_be/src/v/bp_be_calculator/bp_be_regfile.v
black-parrot/bp_be/src/v/bp_be_checker/bp_be_checker_top.v
black-parrot/bp_be/src/v/bp_be_checker/bp_be_detector.v
black-parrot/bp_be/src/v/bp_be_checker/bp_be_director.v
black-parrot/bp_be/src/v/bp_be_checker/bp_be_scheduler.v
black-parrot/bp_be/src/v/bp_be_mem/bp_be_ptw.v
black-parrot/bp_be/src/v/bp_be_mem/bp_be_csr.v
black-parrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
black-parrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf.v
black-parrot/bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache_wbuf_queue.v
black-parrot/bp_be/src/v/bp_be_mem/bp_be_mem_top.v
black-parrot/bp_fe/src/v/bp_fe_bht.v
black-parrot/bp_fe/src/v/bp_fe_btb.v
black-parrot/bp_fe/src/v/bp_fe_icache.v
black-parrot/bp_fe/src/v/bp_fe_instr_scan.v
black-parrot/bp_fe/src/v/bp_fe_mem.v
black-parrot/bp_fe/src/v/bp_fe_pc_gen.v
black-parrot/bp_fe/src/v/bp_fe_top.v
black-parrot/bp_me/src/v/lce/bp_lce.v
black-parrot/bp_me/src/v/lce/bp_lce_req.v
black-parrot/bp_me/src/v/lce/bp_lce_cmd.v
black-parrot/bp_me/src/v/cache/bp_me_cache_dma_to_cce.v
black-parrot/bp_me/src/v/cache/bp_me_cache_slice.v
black-parrot/bp_me/src/v/cache/bp_me_cce_to_cache.v
black-parrot/bp_me/src/v/cce/bp_cce.v
black-parrot/bp_me/src/v/cce/bp_cce_alu.v
black-parrot/bp_me/src/v/cce/bp_cce_arbitrate.v
black-parrot/bp_me/src/v/cce/bp_cce_branch.v
black-parrot/bp_me/src/v/cce/bp_cce_dir.v
black-parrot/bp_me/src/v/cce/bp_cce_dir_lru_extract.v
black-parrot/bp_me/src/v/cce/bp_cce_dir_segment.v
black-parrot/bp_me/src/v/cce/bp_cce_dir_tag_checker.v
black-parrot/bp_me/src/v/cce/bp_cce_gad.v
black-parrot/bp_me/src/v/cce/bp_cce_inst_decode.v
black-parrot/bp_me/src/v/cce/bp_cce_inst_predecode.v
black-parrot/bp_me/src/v/cce/bp_cce_inst_ram.v
black-parrot/bp_me/src/v/cce/bp_cce_inst_stall.v
black-parrot/bp_me/src/v/cce/bp_cce_msg.v
black-parrot/bp_me/src/v/cce/bp_cce_pending_bits.v
black-parrot/bp_me/src/v/cce/bp_cce_reg.v
black-parrot/bp_me/src/v/cce/bp_cce_spec_bits.v
black-parrot/bp_me/src/v/cce/bp_cce_src_sel.v
black-parrot/bp_me/src/v/cce/bp_io_cce.v
black-parrot/bp_me/src/v/cce/bp_cce_fsm.v
black-parrot/bp_me/src/v/cce/bp_cce_wrapper.v
black-parrot/bp_me/src/v/cce/bp_cce_loopback.v
black-parrot/bp_me/src/v/cce/bp_uce.v
black-parrot/bp_me/src/v/wormhole/bp_me_addr_to_cce_id.v
black-parrot/bp_me/src/v/wormhole/bp_me_cce_id_to_cord.v
black-parrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_bidir.v
black-parrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_client.v
black-parrot/bp_me/src/v/wormhole/bp_me_cce_to_mem_link_master.v
black-parrot/bp_me/src/v/wormhole/bp_me_cord_to_id.v
black-parrot/bp_me/src/v/wormhole/bp_me_lce_id_to_cord.v
black-parrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_cmd.v
black-parrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_req.v
black-parrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_lce_resp.v
black-parrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_cmd.v
black-parrot/bp_me/src/v/wormhole/bp_me_wormhole_packet_encode_mem_resp.v
black-parrot/bp_top/src/v/bp_nd_socket.v
black-parrot/bp_top/src/v/bp_cacc_vdp.v
black-parrot/bp_top/src/v/bp_cacc_tile.v
black-parrot/bp_top/src/v/bp_cacc_tile_node.v
black-parrot/bp_top/src/v/bp_cacc_complex.v
black-parrot/bp_top/src/v/bp_sacc_vdp.v
black-parrot/bp_top/src/v/bp_sacc_tile.v
black-parrot/bp_top/src/v/bp_sacc_tile_node.v
black-parrot/bp_top/src/v/bp_sacc_complex.v
black-parrot/bp_top/src/v/bp_cfg.v
black-parrot/bp_top/src/v/bp_core.v
black-parrot/bp_top/src/v/bp_core_complex.v
black-parrot/bp_top/src/v/bp_core_minimal.v
black-parrot/bp_top/src/v/bp_clint_slice.v
black-parrot/bp_top/src/v/bp_io_complex.v
black-parrot/bp_top/src/v/bp_io_link_to_lce.v
black-parrot/bp_top/src/v/bp_io_tile.v
black-parrot/bp_top/src/v/bp_io_tile_node.v
black-parrot/bp_top/src/v/bp_mem_complex.v
black-parrot/bp_top/src/v/bp_multicore.v
black-parrot/bp_top/src/v/bp_unicore.v
black-parrot/bp_top/src/v/bp_tile.v
black-parrot/bp_top/src/v/bp_tile_node.v
black-parrot/bp_top/src/v/bsg_async_noc_link.v
black-parrot/external/basejump_stl/bsg_fsb/bsg_fsb_node_trace_replay.v
black-parrot/bp_be/test/common/bp_be_nonsynth_perf.v
black-parrot/bp_me/test/common/bp_mem.v
black-parrot/bp_me/test/common/bp_mem_transducer.v
black-parrot/bp_me/test/common/bp_mem_delay_model.v
black-parrot/bp_me/test/common/bp_mem_storage_sync.v
black-parrot/bp_me/test/common/bp_cce_mmio_cfg_loader.v
black-parrot/bp_me/test/common/bp_me_nonsynth_cce_tracer.v
black-parrot/bp_me/test/common/bp_me_nonsynth_pkg.vh
black-parrot/bp_me/test/common/bp_me_nonsynth_lce_tracer.v
black-parrot/bp_me/test/common/bp_mem_nonsynth_tracer.v
black-parrot/bp_top/test/common/bp_nonsynth_watchdog.v
black-parrot/bp_top/test/common/bp_nonsynth_cosim.v
black-parrot/bp_top/test/common/bp_nonsynth_host.v
black-parrot/bp_top/test/common/bp_nonsynth_if_verif.v
black-parrot/bp_top/test/common/bp_nonsynth_commit_tracer.v
black-parrot/bp_top/test/common/bp_nonsynth_cache_tracer.v
black-parrot/bp_top/test/common/bp_nonsynth_nbf_loader.v
black-parrot/bp_top/test/common/bp_nonsynth_core_profiler.v
black-parrot/bp_top/test/common/bp_nonsynth_pc_profiler.v
black-parrot/bp_top/test/common/bp_nonsynth_branch_profiler.v
black-parrot/bp_top/test/tb/bp_tethered/wrapper.v
black-parrot/bp_top/test/tb/bp_tethered/test_bp.v
black-parrot/bp_top/test/tb/bp_tethered/testbench.v
one modification to the source is necessary: testbench.v:19 needs to be parameter bp_params_e bp_params_p = e_bp_unicore_cfg
normally the makefile does a textual replacement but if you're running outside their flow you need to do that manually
Jose Renau
@renau
I tried the latest version, and I did not see some of the files. How did you run it? (which git version did you use for black-parrot?)
(Not sure if the latest black-parrot has an issue because I can not find the definition of floatControlWidth once I update the list of verilog files)
Michael Popoloski
@MikePopoloski
this was as of 36fbdd161d2d8a88, which was from back in June
probably the file list has changed slightly since then
of course if you were going to be using this for a while you would figure out how to add slang to their flow instead of hardcoding the file list separately
I was just trying to make sure slang works correctly in general on their codebase
layson-inventor
@layson-inventor
Hello,I want to ask a question.When Verilog is converted into JSON and the module is instantiated, why is the connection information of the port missing?The Verilog source file is as follows:
module two_inst(A);
input A;
M1 inst1 (
.a(A)
);
endmodule
module M1(a);
input a;
endmodule
When we convert it to JSON, the .a(A) is not converted in JSON, is its information lost?
Michael Popoloski
@MikePopoloski
it looks like an oversight, the serialize method simply doesn't write the port connections
should be easy to fix
Michael Popoloski
@MikePopoloski
should be fixed in the latest commit
layson-inventor
@layson-inventor
Thank you very much!
Jose Renau
@renau

I think that I found a bug in slang json. This verilog

module add2(input [6:0] a, input [7:0] b,
  output [8:0] ju
);

  wire signed [6:0] as = a;
  wire signed [7:0] bs = b;

  assign ju = as + bs;

endmodule

Generates this json (just last part)

            "name": "",
            "kind": "ContinuousAssign",
            "addr": 93824996304432,
            "assignment": {
              "kind": "Assignment",
              "type": "logic[8:0]",
              "left": {
                "kind": "NamedValue",
                "type": "logic[8:0]",
                "symbol": "93824996304248 ju"
              },
              "right": {
                "kind": "BinaryOp",
                "type": "logic[8:0]",
                "op": "Add",
                "left": {
                  "kind": "Conversion",
                  "type": "logic[8:0]",
                  "operand": {
                    "kind": "NamedValue",
                    "type": "logic signed[6:0]",
                    "symbol": "93824996302976 as"
                  }
                },
                "right": {
                  "kind": "Conversion",
                  "type": "logic[8:0]",
                  "operand": {
                    "kind": "NamedValue",
                    "type": "logic signed[7:0]",
                    "symbol": "93824996303136 bs"
                  }
                }
              },

The issue is that the ADD is signed because both inputs are signed. The conversion at the left/right operand dest is "logic[8:0]" but it should be "logic signed[8:0]", isn't it?

Jose Renau
@renau

Maybe another way to see the same problem. This verilog file is LEC (yosys) if TEST is set or not

module add2(input signed [6:0] a, input signed [7:0] b,
  output [8:0] ju
);

  `ifdef TEST
  reg signed [8:0] tmp;
  assign tmp = a + b;
  assign ju = tmp;
  `else
  assign ju = a + b;
  `endif

endmodule

But the json when TEST is undefined shows a Conversion:

                "left": {
                  "kind": "Conversion",
                  "type": "logic[8:0]",
                  "operand": {
                    "kind": "NamedValue",
                    "type": "logic signed[6:0]",
                    "symbol": "93824996303336 a"
                  }
Michael Popoloski
@MikePopoloski
ju isn't signed though right?
Jose Renau
@renau
ju is unsigned
When ju is signed, I get the expected result
Michael Popoloski
@MikePopoloski
yeah, I see, the unsignedness is being propagated
Jose Renau
@renau
The issue is that signed or unsigned 'ju', the conversion from logic signed[6:0] to logic[8:0] does not look right because it should be a logic signed[6:0] to logic signed[8:0]
Michael Popoloski
@MikePopoloski
I think that's right, the conversion should just be of the size, not also to unsigned
and then the the whole addition should then be converted to unsigned
Jose Renau
@renau
I think so, we are interfacing slang with LiveHD and some random tests were failing because of that.
Michael Popoloski
@MikePopoloski
yes, there's a very simple reproducer:
module m;
  logic [7:0] foo;
  logic signed [5:0] a = -1;
  logic signed [4:0] b = -2;
  initial begin
    foo = a + b;
    $displayh(foo);
  end
endmodule
this should print fd but in slang currently prints 5d
Michael Popoloski
@MikePopoloski
I committed a fix, let me know if it works for you
Jose Renau
@renau
Thanks,
Let me integrate the new patch, but it looks fine.
Winging
@Winging
Hi,Mike. What's the difference between list and separate list in syntax.txt
Winging
@Winging
I got it that separated_list includes token inside.
Michael Popoloski
@MikePopoloski
yes, that's right
typically a comma
Julien FAUCHER
@suzizecat
Hi there !
Are includes through include some_file.svh and/or the define statements (with backticks that gitter wont render) supported ?
Julien FAUCHER
@suzizecat

I got an error on doing

`define D_ALU_SWAP 3
assign cmp_rev_op   = command[D_ALU_SWAP];

stating that D_ALU_SWAP is undefined.
Given cmd_rev_op is defined as logic and command as logic [7:0]

Michael Popoloski
@MikePopoloski
yes, all preprocessor directives are supported
you're missing a backtick for D_ALU_SWAP?
Julien FAUCHER
@suzizecat
Oh
I'm not yet fully used to SV :sweat_smile:
Michael Popoloski
@MikePopoloski
no problem
Julien FAUCHER
@suzizecat
Yeah, that was my issue, no problem with slang then ! Thanks x)
Michael Popoloski
@MikePopoloski
great!
Julien FAUCHER
@suzizecat
Also, is there a way to have an output without the details of errors messages, like having only the first line of
rtl/sv/alu.sv:49:4: error: cannot assign to a net within a procedural context
                        o_bool_val <= 0;
                        ^~~~~~~~~~
(I'm looking for linter to add to TerosHDL)
Michael Popoloski
@MikePopoloski
not currently but it would be easy to add command line flags that control what kind of output you get
Julien FAUCHER
@suzizecat
Well, I won't be working on that in a short term, but you can take it as a suggestion if it's not much work to do :innocent:
Michael Popoloski
@MikePopoloski
sure, I'll add it to my todo list
Julien FAUCHER
@suzizecat
Great !
Shoreshen
@Shoreshen
hallo may I ask a slang cpp question..
Michael Popoloski
@MikePopoloski
Sure...