Sciss/ScalaCollider

you may have noticed, I pushed a minimal update to ScalaCollider 1.19.0; this (and ScalaCollider-UGens) relaxes the license from GPL to LGPL, allowing to link to it as a library without having to worry about applying the GPL to your own projects.

I also wanted to share some thoughts on a research I have started to conduct...

I have started to map out some directions of development for our sonification platform SysSon -- which you may know uses ScalaCollider at the bottom level. One thing that is interesting to explore is the possibility to decompose complex synth graphs with expensive optional "branches" into actually different synths. Here is a simplified model:

// ---- Unit result ----

If (freq > 100) {
  Out.ar(0, SinOsc.ar(freq))
}

If (freq > 100) {
  Out.ar(0, SinOsc.ar(freq))
} Else {
  freq.poll(0, "freq")
}

// ---- GE result ----

val res: GE = If (freq > 100) {
  SinOsc.ar(freq)
} Else {
  WhiteNoise.ar
}
Out.ar(0, res)

val res: GE = If (freq > 1000) {
  SinOsc.ar(freq)
} ElseIf (freq > 100) {
  Dust.ar(freq)
} Else {
  WhiteNoise.ar
}
Out.ar(0, res)

Currently we can do something like this of course using signal comparators, like

Out.ar(0, SinOsc.ar(freq) * (freq > 100))

or

val freqGt = freq > 100
val res: GE = {
  SinOsc.ar(freq) * freqGt
} + {
  WhiteNoise.ar * (1 - freqGt)
}
Out.ar(0, res)

But these imply that all UGens compute at all times. So for expensive mutually exclusive branches (as they can occur in SysSon), it might be great to decompose this into sub-trees that end up in different synths:

// ---- tree 1 ----
val freq: GE = ???

// ---- tree 2a
val res = SinOsc.ar(freq)

// ---- tree 2b
val res = Dust.ar(freq)

// ---- tree 2c
val res = WhiteNoise.ar

// ---- tree 3 ----
Out.ar(0, res)

This poses multiple challenges, of course. The most basic one, the syntax with which to declare this If, ElseIf, Else structure.
Then how to automatically partition the graph into connected trees.
We would need to inject bus-controls between shared signals.
Imagine that tree 3 also made use of the freq parameter, so there
might be actually quite a bit of wiring going on. And then the
correct real-time control. I am currently thinking of pausing the
synths for the inactive branches, this would still allow the
If conditional expression to run at control rate. An even
smarter UGen graph builder could try to parse the conditional
to see if the graph can be decided already at building time
(scalar condition that can be decided on the client).

So if you have any thoughts on this, I'd like to hear them. The Gitter channel might be the best place for this. At this stage it is not clear whether this branching mechanism will be feasible at all.