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  • Sep 07 09:00

    michaeldaas on development

    ENH: Make sure we get die posit… (compare)

  • Jul 21 13:28
    VincentGuerard commented #132
  • Jul 17 13:53
    themperek commented #132
  • Jul 17 13:53

    themperek on development

    BUG: Fix memory address not inc… BUG: Reverse word reading in ha… (compare)

  • Jul 17 13:53
    themperek closed #132
  • Jun 30 21:33
    themperek edited #133
  • Jun 30 17:28
    coveralls commented #133
  • Jun 30 17:05
    thirono opened #133
  • Jun 30 17:04

    thirono on cleanup-timestamp-modules

    MNT: add Readme for timestamp, … (compare)

  • May 27 12:47

    thirono on tlu_with_longer_data

    ENH: longer tlu data and fix fo… (compare)

  • May 27 11:21

    thirono on tlu_with_longer_data

    ENH: longer tlu data (compare)

  • May 27 08:40

    thirono on development

    (compare)

  • May 26 18:42

    thirono on development

    ENH: add another data format to… (compare)

  • Mar 16 08:01
    themperek commented #132
  • Mar 12 11:22

    laborleben on development

    MAINT: dereference the thread o… (compare)

  • Mar 12 11:17

    laborleben on development

    ENH: put imports and other stuf… (compare)

  • Mar 12 10:55

    laborleben on development

    MAINT: specify Exception (compare)

  • Mar 12 10:42
    laborleben closed #47
  • Mar 12 10:42
    laborleben commented #47
  • Mar 12 10:40
    laborleben closed #51
Tomasz Hemperek
@themperek
We should develop some strategy for version etc. like x.x.y where x.x no API change? Just bugs and small fixes?
Jens Janssen
@laborleben
you are still committing to master... that makes it hard to follow
Jens Janssen
@laborleben
look, no automatic merging possible if you manually bug fix each branch separately
the upstream branch is fixed now, unittest is ok now
Tomasz Hemperek
@themperek
only small stuff
it think it is for bugs and small very small improvements?
not bigger changes to api/functionality
the problem is only if it is the same file
Jens Janssen
@laborleben
concerning seq_gen: is CONF_COUNT / SIZE in bits or bytes?
the code is ambiguous about that
Jens Janssen
@laborleben
exactly this one
Tomasz Hemperek
@themperek
Should probably make 2.0.4 release and 2.0.x branch just for fixes and make 2.1.0 out of development.
Let people know to use 2.0.x branch if they do not need new stuff and minimize problems. for running systems. Any comments?
Jens Janssen
@laborleben
so cherry pick some of the bugfixes and feature? this branching model sound reasonable to me http://nvie.com/posts/a-successful-git-branching-model/
I agree with you. But I'd like to see a 2.1.0 release very soon. pyBAR and CCPDv4 also using 2.1.0 development right now
Jens Janssen
@laborleben
the documentation is missing the anaconda part. for reasons?
Tomasz Hemperek
@themperek
no
feel free to add (this in principle is not needed)
Jens Janssen
@laborleben
ok thanks
Tomasz Hemperek
@themperek
I will work on TLU today
Tomasz Hemperek
@themperek
Tomasz Hemperek
@themperek

Hack to install basil via pip:
master:

pip install -e "git+https://github.com/SiLab-Bonn/basil.git#egg=basil&subdirectory=host"

development:

pip install -e "git+https://github.com/SiLab-Bonn/basil.git@development#egg=basil&subdirectory=host"
David-Leon Pohl
@DavidLP
top
Jens Janssen
@laborleben
2.1.1 release soon?
I'd like to use with pyBAR 2.1
Tomasz Hemperek
@themperek
fix tdc and do it
Jens Janssen
@laborleben
SiUART is also a bit messy
i do not know why he closed this?
Jens Janssen
@laborleben
v2.1.1 release?
I prepared master branch
Tomasz Hemperek
@themperek
new release?
Jens Janssen
@laborleben
0.0.1 release? from my side OK
v2.1.3 then?
Tomasz Hemperek
@themperek
yes
Tomasz Hemperek
@themperek
data corruption was proabably comming from this: SiLab-Bonn/basil@70742a4
Jens Janssen
@laborleben
interesting
i moved pysilibusb to github https://github.com/SiLab-Bonn/pySiLibUSB
Jens Janssen
@laborleben
are you sure it will solve the problem? I doubt, because we read out anyway modulo of 4
Jens Janssen
@laborleben
//BASIL bus mapping
wire [15:0] BUS_ADD;
assign BUS_ADD = ADD - 16'h4000;
wire BUS_RST, BUS_CLK, BUS_RD, BUS_WR;
reg RD_B_FF;
always @ (posedge BUS_CLK)
begin
RD_B_FF <= RD_B;
end
assign BUS_RD = (~RD_B & RD_B_FF);
assign BUS_WR = ~WR_B;
assign BUS_CLK = FCLK_IN;
tested but not working :-(
but when I change
always @ (posedge BUS_CLK)
begin
if (BUS_ADD == 4 && BUS_RD)
CONF_SIZE_BYTE_BUF <= CONF_SIZE_BYTE;
end
to negedge it works
strange
Tomasz Hemperek
@themperek
We do not have test for TDC?
draft v2.4.0
more things to add
Tomasz Hemperek
@themperek
want to make v2.4.1 (draft ready) Any comments?
Jens Janssen
@laborleben
need some testing
Tomasz Hemperek
@themperek
tested with epcb01 witch did not work before on FW15 (48MHz) and FW8 (24MHz)
also on 2 other project and sram test