Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Repo info
Activity
  • Jul 06 18:11

    MarcoVogt on SiTCP_10G

    ENH: Automatically handle SiTCP… (compare)

  • Jul 06 17:57

    MarcoVogt on SiTCP_10G

    ENH: Add SiTCP version check (compare)

  • Jul 06 07:25
    themperek commented on c41118f
  • Jul 05 18:25
    MarcoVogt commented on c41118f
  • Jul 04 13:46
    themperek commented on c41118f
  • Jul 04 12:52

    MarcoVogt on SiTCP_10G

    ENH: KC705 example with 10G SFP… (compare)

  • Jul 04 12:31

    MarcoVogt on SiTCP_10G

    (compare)

  • Jun 25 19:56

    themperek on master

    Update version to 3.2.1dev0 (compare)

  • Jun 25 19:48

    themperek on v3.2.0

    (compare)

  • Jun 25 15:39

    themperek on master

    Update version to 3.2.0 (compare)

  • Jun 23 11:37

    themperek on master

    Update simulation framework - m… (compare)

  • Jun 23 11:37
    themperek closed #163
  • Jun 23 10:52
    codecov[bot] commented #163
  • Jun 23 10:51
    codecov[bot] commented #163
  • Jun 23 10:49
    codecov[bot] commented #163
  • Jun 23 10:48
    codecov[bot] commented #163
  • Jun 23 10:48
    codecov[bot] commented #163
  • Jun 23 10:41
    codecov[bot] commented #163
  • Jun 23 10:41
    themperek synchronize #163
  • Jun 23 10:41

    themperek on Update-simulation-framework

    Update simulation framework - m… (compare)

Tomasz Hemperek
@themperek
We should develop some strategy for version etc. like x.x.y where x.x no API change? Just bugs and small fixes?
Jens Janssen
@laborleben
you are still committing to master... that makes it hard to follow
Jens Janssen
@laborleben
look, no automatic merging possible if you manually bug fix each branch separately
the upstream branch is fixed now, unittest is ok now
Tomasz Hemperek
@themperek
only small stuff
it think it is for bugs and small very small improvements?
not bigger changes to api/functionality
the problem is only if it is the same file
Jens Janssen
@laborleben
concerning seq_gen: is CONF_COUNT / SIZE in bits or bytes?
the code is ambiguous about that
Jens Janssen
@laborleben
exactly this one
Tomasz Hemperek
@themperek
Should probably make 2.0.4 release and 2.0.x branch just for fixes and make 2.1.0 out of development.
Let people know to use 2.0.x branch if they do not need new stuff and minimize problems. for running systems. Any comments?
Jens Janssen
@laborleben
so cherry pick some of the bugfixes and feature? this branching model sound reasonable to me http://nvie.com/posts/a-successful-git-branching-model/
I agree with you. But I'd like to see a 2.1.0 release very soon. pyBAR and CCPDv4 also using 2.1.0 development right now
Jens Janssen
@laborleben
the documentation is missing the anaconda part. for reasons?
Tomasz Hemperek
@themperek
no
feel free to add (this in principle is not needed)
Jens Janssen
@laborleben
ok thanks
Tomasz Hemperek
@themperek
I will work on TLU today
Tomasz Hemperek
@themperek
Tomasz Hemperek
@themperek

Hack to install basil via pip:
master:

pip install -e "git+https://github.com/SiLab-Bonn/basil.git#egg=basil&subdirectory=host"

development:

pip install -e "git+https://github.com/SiLab-Bonn/basil.git@development#egg=basil&subdirectory=host"
David-Leon Pohl
@DavidLP
top
Jens Janssen
@laborleben
2.1.1 release soon?
I'd like to use with pyBAR 2.1
Tomasz Hemperek
@themperek
fix tdc and do it
Jens Janssen
@laborleben
SiUART is also a bit messy
i do not know why he closed this?
Jens Janssen
@laborleben
v2.1.1 release?
I prepared master branch
Tomasz Hemperek
@themperek
new release?
Jens Janssen
@laborleben
0.0.1 release? from my side OK
v2.1.3 then?
Tomasz Hemperek
@themperek
yes
Tomasz Hemperek
@themperek
data corruption was proabably comming from this: SiLab-Bonn/basil@70742a4
Jens Janssen
@laborleben
interesting
i moved pysilibusb to github https://github.com/SiLab-Bonn/pySiLibUSB
Jens Janssen
@laborleben
are you sure it will solve the problem? I doubt, because we read out anyway modulo of 4
Jens Janssen
@laborleben
//BASIL bus mapping
wire [15:0] BUS_ADD;
assign BUS_ADD = ADD - 16'h4000;
wire BUS_RST, BUS_CLK, BUS_RD, BUS_WR;
reg RD_B_FF;
always @ (posedge BUS_CLK)
begin
RD_B_FF <= RD_B;
end
assign BUS_RD = (~RD_B & RD_B_FF);
assign BUS_WR = ~WR_B;
assign BUS_CLK = FCLK_IN;
tested but not working :-(
but when I change
always @ (posedge BUS_CLK)
begin
if (BUS_ADD == 4 && BUS_RD)
CONF_SIZE_BYTE_BUF <= CONF_SIZE_BYTE;
end
to negedge it works
strange
Tomasz Hemperek
@themperek
We do not have test for TDC?
draft v2.4.0
more things to add
Tomasz Hemperek
@themperek
want to make v2.4.1 (draft ready) Any comments?
Jens Janssen
@laborleben
need some testing
Tomasz Hemperek
@themperek
tested with epcb01 witch did not work before on FW15 (48MHz) and FW8 (24MHz)
also on 2 other project and sram test