About chisel and spinal i have something to share
I'm a 10 years verilog guys, at first, i used the chisel in my ic work for a period of time,
and Then found spinalHDL by a chance. after spent one week to know spinalhdl, I was very sure move from chisel to Spinal.
Although compared with Verilog, chisel gives me a taste of the power of real parameterization,
But Why I abandoned Chisel and move to spinalHDL with a simple reason:
chisel/Rocket have too many low-level design errors.
All of this points to its team background, most of them come from school, They may be more academic and creative, but they are relatively inexperienced in engineering
some people may disagree with me, but even if there is a little HW engineer background
the following mistakes should never be made
- cant ignore such important and basic things as asynchronous reset,
- cant missing basic
caseexpression(they use if/else instead, too ugly) - the design of rocketChip global
implicitparameterpis so terrible
Some designs are just wishful thinking or Academic experimental
- iotest, no practical toys. It seems that iotest2 realize that and on the right track
- firrtl, it just make design and debug more complex and difficult then do nothing good
and you will find Both chisel-source-code and generated verilog code lack readability, make you mad
Maybe the SpinalHDL not top perfect, So far, I haven't found any very serious low-level problems,
Spinal have complete documentation and readable source code. More friendly to IC-HW engineers.
and i found spinal have better tasty :grinning:
here is simple compare for little detail
at last ,We have recently developed a GNSS positioning chip with spinalHDL, so don't worry about whether it is suitable for real IC project.
@bellaz89 I am nowhere near proficient enough on both of them to be able to feel strongly about this but here is a bit of my experience. A lot of this might not even a limitation of Chisel but a limitation of myself. I have tried a significant project in Chisel in my work, but then just went back to Verilog when my time for experimentation ran out. I've not tried anything with SpinalHDL outside some workshops. I did however have brief hurdle with Chisel that I don't think I'll have with SpinalHDL when I have time to try this again:
- Tristate. Chisel doesn't really support this. SpinalHDL has a full page describing this https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Libraries/IO/tristate.html. Same issue with inout signals. I had to infer my bidirectional buffer in Quartus rather than just using inout and being done with it. Doesn't block anything, but it is just.... ugh.
- PeekPokeTester. For reasons that are beyond me, the Peekpoketester can only drive inputs on falling edge clocks. Maybe there is some way around this, but it really wasn't clear to me how that could be done. Not sure how iotest2 works on this regard but SpinalSim seems to be much superior and I smile when I look at this page https://spinalhdl.github.io/SpinalDoc-RTD/SpinalHDL/Simulation/clock.html . Though, again, something I need to try for myself before giving SpinalHDL the victory here.
- Overcomplicated references. I want to do something simple, create a memory mapped Avalon Bus Slave. So then I start looking for examples on how to set up a memory mapped bus slave. Crickets. Then I find a couple of processors and they use this RegisterRouter module, that is a library of a particular CPU (rocketchip) instead of being part of the Chisel framework. Still way too complicated, uses some TileLink fabric, with some options for AXI4. Then I look the AXi4 implementation. Stacked, still can't follow with my lackluster Scala knowledge. I find another less complicated RegisterRouter example in SiFive repo, uses wishbone, much nicer. Still, it is hard to follow the crumbs of how things are supposed to be used across several different repos. Maybe one day it will be a simpler undertaking. On SpinalHDL, there is a very simple setup in one of the SpinalHDL youtube videos that just builds a geenric slave with a bus factory and implements the register interface. Done. I expect this to be simple, and the video + source code show it is simple. When I look at the SpinalLib that has these bus implementations (one of which was Avalon!), it is much simpler to follow. I actually tried to implement the SpinalHDL Avalon Bus implementation in Chisel, but ran into all sort of issues. I couldn't even write the .asMaster and .asSlave implementations (though that' s probably a problem with me, not with Chisel). Anyways, I digress. It just seems like SpinalHDL is holding my hand a lot more with the application that I am in. Some of the constructs like BusFactory and Flow are not only nice and useful, but actually highlight how actual OOP Scala can be used for hardware generation. Whenever I look at the rocketchip libraries in Chisel I just see a bunch of clever mappings with organization going all over the place and just drown.
Chisel has a lot going for it though. SiFive is also a really cool reference if I were to sit and try to understand it one day. There is BOOM, Rocketchip repos, and many more videos online talking about Chisel. There's a few (underdocumented) libraries that might be worth looking into like diplomacy, dsptools, tilelink. Chisel bootcamp is also a big thing that was essential for me to actually get started with all of this. They even have a book with some neat examples too. SpinalHDL only has a rusty SpinalWorkshop and a few examples in the documentation, but not much other than that. I had a much harder time finding examples and references in SpinalHDL, which is why I went the Chisel route in the first place. At the "I don't know Scala at all" level, Chisel held my hand much more.
@pcesar22 Your experience is so real.
Overcomplicated references. I want to do something simple, create a memory mapped Avalon Bus Slave .....
I can't damn agree more with these experience and feelings.
Chisel is really more famous, but most because of Berkeley and RISCV, It is the first language to provide a feasibility of develeping HDL based on Scala . But What Chisel means to me was that gave me a ladder to SpinalHDL :grinning:
