Im trying to do a cross compilation of a linux module on fpga under linux v5.10.1 (SpinalSaxon)
the toolchain is version = 8.3.0-1.2
I downloaded v5.10.1 and extracted the kernelheaders to compile with ,
when loading, it tells me invalid ELF headers on the target
Invalid ELF headers.
on buildroot , kernel headers are same as kernel being build .
I tried to cross compile a helloworld.c with riscv-none-embed-gcc , the same toolchain as the Saxonspinal but i have
helloworld [201]: unhandled signal 4 code 0x1 at 0x000100ac in helloworld[10000+3000] on the target
what is the problem ?
thank you
hey,
Let's suppose I did something like this :
val testApbBmb = BmbToApb3Generator(SizeMapping(0x38000, 4 KiB))
testApbBmb.apb3Config.load(Apb3Config(
addressWidth = 32,
dataWidth = 32
))
val testApbArea = Handle(new Area {
val myreg = Reg(UInt(32 bit)).init(U"x03020100")
val busCtrl = Apb3SlaveFactory(testApbBmb.output)
busCtrl.readAndWrite(myreg, address = 0x8000)is it normal, that accessing to the address where the apb is mapped ( here is 0x10038000 ) produces an address on PADDR = 0x8000, instead of zero ?
#prepare linux headers to Cross Compile module
#!/bin/bash
export PATH=~/opt/xpack-riscv-none-embed-gcc/bin:$PATH
Prefix=riscv-none-embed-
KernelHeader=$PWD/KernelHeaders/
cd /home/tiempo/Documents/LarbiIntership/Ipc_driver/compiled/cross_com/linux
make ARCH=riscv CROSS_COMPILE=$Prefix O=$KernelHeader mrproper;
make ARCH=riscv CROSS_COMPILE=$Prefix O=$KernelHeader defconfig;
make -j 8 ARCH=riscv CROSS_COMPILE=$Prefix O=$KernelHeader modules_prepare;If KERNELRELEASE is defined, we've been invoked from the kernel build system
# and can use its language
ifneq ($(KERNELRELEASE),)
obj-m := tiempo_ipc.o
#Otherwize we were called directly from the command line ; invlok kbuild system
else
KERNELDIR ?="./KernelHeaders/"
PWD := $(shell pwd)
.PHONY : modules
modules:
$(MAKE) -C $(KERNELDIR) M=$(PWD) modules
endif
.PHONY: clean
clean:
$(MAKE) -C $(KERNELDIR) M=$(PWD) clean
CFLAGS_tiempo_ipc.o := -DDEBUG#!/bin/bash
export PATH=$PATH:/home/tiempo/opt/xpack-riscv-none-embed-gcc/bin
#build module
make ARCH=riscv CROSS_COMPILE=riscv-none-embed-
#info module
echo""
echo "module informations"
modinfo tiempo_ipc.ko
1 reply
twoCycleRam = false,
twoCycleCache = true,
IBusCachedPlugin =>
injectorStage = true,
i have to rebuild and load every time i change something on code . and i have to do some stuff i user space so i need to cross compile codes cause we dont have compiler on buildroot
the ibus will still be active
Does this really matter? If the core is disabled (or more like frozen), doesn't pc simply stay at whatever value it was at that time? If so, the IBus memory would simply keep feeding the same rsp back to the core and the core would simply continue from where it left off after being enabled again.
The DBus interface is another thing, though, since there's muxing involved.
Basicaly, instead of addressWidth = 32, should have addressWidth = 12, ?
@Dolu1990 . Yes by reducing the address width it works, but if I imagine a scenario where the APB is mapped to an address that doesn't end with zeros, then it will not work. Anyway, I just wanted to be sure about this.
Thank you for your response :)
Does this really matter?
Yes, because the i$ will miss the bus response, and will be stuck there forever
the IBus memory would simply keep feeding the same rsp
But some additional logic will be required
And wait that all ongoing transactions are done
and finaly you can clear the clock enable
Is there any way to generate register array in verilog? For example if I write below in spinalHDL
val data = Vec(UInt(8 bits), 1024)I want it generate register array in verilog as shown below:
reg [7:0] data[1024];Not sure if Vec has some configuration to do that?
Basically Vec generates data_1, data_2, data_3......data_1024 and make generated verilog file too long.