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  • Jan 15 19:33
    dotcypress commented #364
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    dotcypress commented #364
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    dotcypress commented #364
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  • Jan 13 22:59
    Dolu1990 commented #364
  • Jan 13 21:08

    Dolu1990 on dev

    Stream.swapPayload added UInt.twoComplement fix simplify SpinalEnumCraft with l… (compare)

  • Jan 12 17:42
    dotcypress edited #364
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  • Jan 11 15:26

    svancau on bmbl2cache

    Add L2 Cache (WIP, not working) (compare)

  • Jan 11 11:36

    Dolu1990 on dev

    max bit width 4095 -> 4096 WS(write set) bug fixed Merge pull request #363 from ji… (compare)

STOPNOAnime
@STOPNOAnime
Ignore my issues. Everything works now xd
cinifr
@cinifr
hi all, I am a newer of vexriscv, I want to use ethernet on vexriscv(Murax). where can i get a demo ?
Dolu1990
@Dolu1990
@cinifr There is no ethernet yet on murax
but
there is RMII and MII MAC already implemented
cinifr
@cinifr
yes,I have saw it, but I cant use it。Can I get a demo of using mac of spinalhdl lib?
Dolu1990
@Dolu1990
the only demo is based on BMB memory bus, and in the Generator framwork
so not very much murax compatible
but basicaly, the things that you have to do is to instanciate the Mac, connect it to APB like it is done for BMB, but with the Apb3SlaveFactory
And then strap the apropriated phy
cinifr
@cinifr
thanks. I'll give it a try.
Andreas Wallner
@andreasWallner

I have a small problem with the InOutWrapper: I'm currently using SpinalHDL to write peripherals that will be integrated into a Zynq design, the SpinalHDL design will not be the toplevel. I wanted to use InOutWrapper to convert some TriState signals to analog, but it seems Vivado is not happy with inferring the IOBUF if the assignments that the InOutWrapper generates do not happen on the toplevel. If I manually instance the IOBUF everything works nicely.

I therefore wanted to extend the InOutWrapper such that the IOBUFs that are needed are automatically generated as Blackboxes instead of being inferred - but I'm failing there, it seems my understanding of Scala/Spinal are not sufficient ATM...

My current try for the rework section of TriState types:

case bundle: TriState[_]  if bundle.writeEnable.isOutput  => {
  val newIo = inout(Analog(bundle.dataType)).setWeakName(bundle.getName())
  val bufs = Array.fill[IOBUF](bundle.dataType.getBitsWidth)(IOBUF())
  bundle.setAsDirectionLess.unsetName().allowDirectionLessIo
  (bufs zip bundle.read.asBits.asBools zip bundle.write.asBits.asBools) map {
    case ((buf, r), w) =>
      println(buf, r, w)
      buf.I := w
      r := buf.O
      buf.T := bundle.writeEnable
  }
}

Leads to an error during generation:

[error] NO DRIVER ON (toplevel/??? :  Bool), defined at
[error]     andreasWallner.Test$$anon$1$$anonfun$3.apply(iowrapper.scala:84)
[error]     andreasWallner.Test$$anon$1$$anonfun$3.apply(iowrapper.scala:84)
[error]     spinal.lib.io.TriState.<init>(TriState.scala:7)
[error]     andreasWallner.Test$$anon$1.<init>(iowrapper.scala:84)
[error]     andreasWallner.Test.<init>(iowrapper.scala:83)
....

How would I correctly implement this?

My test component is just
case class Test() extends Component {
  val io = new Bundle {
    val tri = master(TriState(Bool))
  }
  io.tri.write := True
  io.tri.writeEnable := io.tri.read
}
Dolu1990
@Dolu1990
which signal exactly has no driver ?
seems to be the read or write of Tristate at the toplevel
Ahhh got it
read.asBits.asBools
Basicaly
asBits create a new signal driven by read
so if you assign the result of asBits by stuff it will not assign the "read" signal, but its copy
that's your issue
Winston Lowe
@wel97459
Are there any examples of using lib.com.i2c, I'm totally lost.
Dolu1990
@Dolu1990
Winston Lowe
@wel97459
@Dolu1990 thanks
Andreas Wallner
@andreasWallner
@Dolu1990 thanks a bunch, solved that using assignFromBits, I know have a problem connecting the newly created analog port to the IOBUF instance but I'll try to figure that out for myself for a bit longer... ;-)
pointcheck
@pointcheck
Can SaxonSoc (or any other written in SpinalHDL) work with MT41K64M16 SDRAM which is DDR3 ? I can see there is support for some Micron's SDRAM chips, but not sure if all SDRAMs use the same protocol.
Dolu1990
@Dolu1990
@pointcheck https://github.com/SpinalHDL/SaxonSoc/tree/dev-0.2/bsp/digilent/ArtyA7SmpLinux works with MT41K128M16JTs which is pretty close
pointcheck
@pointcheck
Dolu1990, that's good, thanks. I finally made I/D cache working with Murax SoC also with my Sram module on Olimex ICE40HX8K board. A distinguished feature is per-byte writes to SRAM IC that has both BHE# and BLE# signals tied to ground. I.e. it reads 16 bits, modifies appopriate byte then writes 16 bits back. Per-byte IO is slow of course (takes 5 clocks), but it works and one can use sprintf() and other libc string functions now :). Can it be of any good to publish my work ?
Dolu1990
@Dolu1990

@pointcheck Cool ^^

I'm personnaly all the way into Linux softcore configs, but likely others might be interrested

pointcheck
@pointcheck
Dolu1990, can I send you a patch for verification ?
Dolu1990
@Dolu1990
what would you like to verify exactly ?
pointcheck
@pointcheck
Dolu1990, just to check it complys to SpinalHDL standards :)
Dolu1990
@Dolu1990
I can take a refractoring look
pointcheck
@pointcheck
good, I will try to brush it a little and send you a diff
My next step in learning is to try running Linux on OrangeCrab board. It has ECP5-25F, 1M Flash, 128M DDR3, SDCARD and USB directly connected to ECP5. That is why I asked about DDR3 support in SaxonSoc.
Dolu1990
@Dolu1990
There is support for DDR3 for Artix 7 FPGA
but three is no phy layer for ECP5
pointcheck
@pointcheck
I dont quite understand, what is phy layer ? why same code cannot be used for ECP5?
Dolu1990
@Dolu1990
the controller itself is the same
the phy is the part which interface the pins
it has close to zero logic, but many FPGA IO primitive instanciations
io delay, DDR io with gearboxes
stuff like that
pointcheck
@pointcheck
Dolu1990, I'm cloning SaxonSoc right now, have to investigate it for a while to get understanding of what you say. The question is, does it use Yosys/nextpnr to compile binary for Artix, or does it use propretary stuff at some point to deal with timings ?
Dolu1990
@Dolu1990
It currently use vivado for Artix7
pointcheck
@pointcheck
not good :(
Dolu1990
@Dolu1990
some attempts were made to use yosys : SpinalHDL/SaxonSoc#57
pointcheck
@pointcheck
anyways, my goal is ECP5 at the moment, not Artix7 :)
yuqi-ali
@yuqi-ali
@Dolu1990 if i want to use a latch in my design ,how to enable SpianlHDL to generate it