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  • 13:40

    Dolu1990 on dev

    Fix SpiXdrMasterCtrl full dupleā€¦ (compare)

  • Dec 13 23:50
    Dolu1990 commented #243
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  • Dec 12 19:50
    bellaz89 commented #245
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bellaz89
@bellaz89
@Dolu1990 Cool! I have an Arty Z7. I will test Saxon onto it then
Dolu1990
@Dolu1990
but i need to document things a bit
to boot from the SDCARD
ahhhh probably Arty Z7 would be quite different as that's a zynq :/
bellaz89
@bellaz89
Well, probably I will need to check the differences (might be a nice christmas task :D ) ..
Dolu1990
@Dolu1990
mainly, you won't have access to the DDR pin from the FPGA, but a AXI bus
bellaz89
@bellaz89
Yeah, probably some BlackBoxing is going to be required
bellaz89
@bellaz89
Also probably I won't be able to boot from the onboard SDCard .. Maybe an extension module is going to be required
Michael Meier
@distributed
Hey guys. I just used SpinalHDL to build a simple Apb3 Slave. Now I tried to integrate it into a Microsemi Libero (be gentle with me...) build. A problem that pops up quickly during synthesis is that the generated PADDR is of type unsigned, however Libero expects a std_logic_vector.
One conceivable way to work around this would be this: Define a new Bundle that has PADDR as Bits and use it to wrap the APB in it. This way, Libero should see a std_logic_vector for PADDR and be happy. Do you have any other suggestions?
Also: Is my presented approach sane and doable?
bellaz89
@bellaz89
Well, at the end bits will remain bits... For sure your approach will work even if you will have to redefine the Apb3 bus again
can't you use a conversion function on the generated code ? https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html
*in
bellaz89
@bellaz89
I mean.. in the vhdl source that uses the spinalhdl-generated component
Or do you need to integrate and use an existing APB3 VHDL component in SpinalHDL?
Michael Meier
@distributed

Well, at the end bits will remain bits... For sure your approach will work even if you will have to redefine the Apb3 bus again

Which makes it only sadder ;)

The SpinalHDL-generated file is integrated into a Libero project. It has a clunky clickable bus interface generator. In order to plug a VHDL file into a such a bus, PADDR needs to be std_logic.
bellaz89
@bellaz89
Well.. then I suppose you either have to wrap everything in spinalHdl as you said or doing it making a support VHDL component
Michael Meier
@distributed
I could do the adaption in Spinal, then I'd declare a new APB-like Bundle that has Bits for PADDR so the generated code will have std_logic_vector. Or I make a small wrapper VHDL file that performs the conversion. Though of course that leads to endless wiring because I need to route all the other signals besides the bus as well.
bellaz89
@bellaz89
yes :)
BTW there is also the possibility to feed a configuration to the source generation that tells to generate stdlogicvectors at the toplevel
onlyStdLogicVectorAtTopLevelIo
bellaz89
@bellaz89
It should work and you won't need to change anything
And you will generate the code using something like:
Spinal(new SpinalConfig(mode = VHDL,  onlyStdLogicVectorAtTopLevelIo = true))(new YourComponent)
instead of
SpinalVhdl(new YourComponent)
Michael Meier
@distributed
Oh, very nice. Thankss for the onlyStdLogicVectorAtTopLevelIo tip!
I am also trying the wrap-in-SpinalHDL approach, however I am stuck.

I define this class:

case class LiberoApb3(config: Apb3Config) extends Bundle with IMasterSlave {

  val PADDR      = Bits(config.addressWidth bits)
  val PSEL       = Bits(config.selWidth bits)
  val PENABLE    = Bool
  val PREADY     = Bool
  val PWRITE     = Bool
  val PWDATA     = Bits(config.dataWidth bits)
  val PRDATA     = Bits(config.dataWidth bits)
  val PSLVERROR  = if(config.useSlaveError) Bool else null

  override def asMaster(): Unit = {
    out(PADDR, PSEL, PENABLE, PWRITE, PWDATA)
    in(PREADY, PRDATA)
    if(config.useSlaveError) in(PSLVERROR)
  }

  def >> (sink: Apb3): Unit = {
      assert(this.config.selWidth == sink.config.selWidth, "APB3 mismatch sel width")

      sink.PADDR   := this.PADDR.resized.asUInt
    sink.PSEL    := this.PSEL
    sink.PENABLE := this.PENABLE
    this.PREADY  := sink.PREADY
    sink.PWRITE  := this.PWRITE
    sink.PWDATA  := this.PWDATA
    this.PRDATA  := sink.PRDATA

    if(PSLVERROR != null) {
      this.PSLVERROR := (if (sink.PSLVERROR != null) sink.PSLVERROR else False)
    }
  }

}

Which is shamelessly ripped off Apb3.

Intending to use it like this:

    val io = new Bundle {
        val bus = slave(LiberoApb3(OPBSys.getApb3Config))
    }

    val apbBus = slave(Apb3(OPBSys.getApb3Config))
    io.bus >> apbBus

However compiling fails with:

[error] HIERARCHY VIOLATION : (toplevel/apbBus_PADDR : in UInt[12 bits]) is driven by (toplevel/??? :  UInt[? bits]), but isn't accessible in the toplevel component.
When I remove the io.bus >> apbBus and only assign the outputs (PREADY, PRDATA, PSLVERR) it compiles. Then I see that apbBus - the one I don't intend to expose - is present in the port list.
bellaz89
@bellaz89
MM port direction should be defined only in the Component interface bundle
what if you remove slave from scala val apbBus = slave(Apb3(OPBSys.getApb3Config))
Michael Meier
@distributed
Now it compiles.
Thank you!
I am not sure I can follow the rationale of the fix though. My guess is this: removing slave removes in ond out on the signals. Signals without these in/out are considered internal. This is why then the internal bus doesn't appear on the external interface any more. Correct?
bellaz89
@bellaz89
I think so. But for these details you have to ask @Dolu1990
Michael Meier
@distributed
OK :) Maybe he'll read it here?
Dolu1990
@Dolu1990
@distributed That's right, but just causes is inverted, basicaly, slave apply the in/out to the bus
Michael Meier
@distributed
Given that I haven't written neither Scala nor SpinalHDL until 24 hours ago, I feel surprisingly productive,.
Dolu1990
@Dolu1990
How is that possible XD ?
why were on which languages before ?
Michael Meier
@distributed

How is that possible XD ?

You can take it as a compliment - or contrast it with endless wiring sessions and keyboard chording for just the right flavor of copy-paste when trying to implement something in VHDL.

Daily I use Go, C, C++ and then VHDL whenever I come near hardware. Plus a few sprinklings of whatever else comes up, like e.g. Lua or Python.
Dolu1990
@Dolu1990
Ahhhh holly world, i got it now
Now i remember the name ^^
Michael Meier
@distributed
Yes, the holy world. Though Go is already heresy.
Hehe.