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  • Aug 12 13:49

    Dolu1990 on dev

    Add Axi4ToAxi3 bridge (compare)

  • Aug 12 09:41

    Dolu1990 on dev

    SpinalSim bring back seed messa… (compare)

  • Aug 12 09:40

    Dolu1990 on dma

    SpinalSim bring back seed messa… (compare)

  • Aug 11 15:49

    Dolu1990 on dma

    DmaSg add selfRestartCapable op… (compare)

  • Aug 11 15:41

    Dolu1990 on dma

    dmaSg improve memory core timin… (compare)

  • Aug 11 15:14

    Dolu1990 on dma

    dmaSg improve FMax (compare)

  • Aug 11 14:56

    Dolu1990 on dma

    DmaSg improve input stream timi… (compare)

  • Aug 11 12:59

    Dolu1990 on dma

    DmaSg improve timings by having… (compare)

  • Aug 10 22:10

    Dolu1990 on dma

    Add the ability to read the cha… (compare)

  • Aug 07 17:51

    Dolu1990 on dma

    Fix Bsb tstrb into tkeep DmaSg … (compare)

  • Aug 07 11:20

    Dolu1990 on dma

    Add Bsb sparse Up/down sizers A… Add Bsb bridges tests DmaSg enable smaller stream test (compare)

  • Aug 07 08:52

    Dolu1990 on dma

    dmasg ctrl can now read pending… (compare)

  • Aug 06 22:05

    Dolu1990 on dma

    DmaSg add channel fixed buffer … (compare)

  • Aug 06 20:02

    Dolu1990 on dma

    DmaSg add half completion inter… (compare)

  • Aug 06 11:54

    Dolu1990 on dma

    Fix BmbUpSizerBridge when write… (compare)

  • Aug 05 18:23

    Dolu1990 on dma

    Dma now do byte accesses relax … (compare)

  • Aug 05 12:49

    Dolu1990 on dma

    Nameable add overrideLocalName Axi4SpecRenamer add Bsb support add DmaSg to regressions (compare)

  • Aug 05 11:52

    Dolu1990 on dma

    Fix BmbContextRemover DmaSg make tester reusable for … (compare)

  • Aug 04 17:31

    Dolu1990 on dma

    DmaSg channels can now have a s… (compare)

  • Aug 04 11:50

    Dolu1990 on dma

    Add BmbSourceRemover FixBmbToAxi4Bridge DmaSg improve timings (compare)

Paulo Costa
@pcesar22
thanks! : )
Paulo Costa
@pcesar22
Correction "I had to infer my bidirectional buffer in Quartus..." ---> " I had to instantiate my bidirectional buffer in Quartus and use a black box in Chisel"
saahm
@saahm
also i remember that chisel was mainly build around the goal of having riscv generators
so it started very specific
Paulo Costa
@pcesar22
@jijingg I'm having this issue that jupyter gets stuck on "kernel starting... please wait". I think it has to do with java version. What java version are you using?
@saahm I didn't know htat, but that is very much in line with my findings. Chisel didn't seem to branch out anywhere else other than the big RISCV specific stuff
Paulo Costa
@pcesar22
Fixed it by changing to java 8
saahm
@saahm
its fast and early results bootstrapped some riscv projects, was neat
jijingg
@jijingg

@pcesar22 Your experience is so real.

Overcomplicated references. I want to do something simple, create a memory mapped Avalon Bus Slave .....

I can't damn agree more with these experience and feelings.

Chisel is really more famous, but most because of Berkeley and RISCV, It is the first language to provide a feasibility of develeping HDL based on Scala . But What Chisel means to me was that gave me a ladder to SpinalHDL :grinning:

bellaz89
@bellaz89
Thanks @pcesar22 . Yes, Bus functionalities are quite cool in Spinal.
bellaz89
@bellaz89
For my PhD I am developing a VexRiscV based controller. For that I needed to write a bunch of computation accelerators. I was really surprised how easy is to attach a memory mapped peripheral to the processor. And the most satisfying thing is that I am able to simulate the entire SoC running compiled programs on top of that.
For the next step I planned to simulate a closed feedback loop using Apache common math ODE package to describe my controlled system.
I really love SpinalSim :)
saahm
@saahm
all out of one bash terminal
the dream of fpga toolflow
VexRiscV is featured on hackaday btw (https://hackaday.com/2020/07/12/softcore-cpu-comparison/)
jijingg
@jijingg
@bellaz89 @pcesar22 the online Spinal-bootcamp Binder is avaliable now :)
bellaz89
@bellaz89
@jijingg Cool thanks :D , I will spread it as much as I can
MM
bellaz89
@bellaz89
I still get Could not find a kernel matching Scala. Please select a kernel:
is it normal?
Dolu1990
@Dolu1990
@jijingg i juste tried from my phone ( in travel ), but it seem that jupyter can’t get a scala kernel (on the binder)
Did i missed something ? Never used jupyter XD
Hoo forget about it, i were in the preview ^^
Winston Lowe
@wel97459
@jijingg that's cool
bellaz89
@bellaz89
Ok, I was able to run it too. Cool!
Also you did quite a thing doing all the images
Oron Port
@soronpo
It's really cool that this actually works on my phone
jijingg
@jijingg
thanks all <3, for the reason of my bad english, there may be a lot of flaws there. please correct me. If someone can complete other chapters, I think people will love you , hah ^^
@Dolu1990 can it work now ? github seems to have crashed for half an hour just now
Dolu1990
@Dolu1990
It work ^^
Georgelau-2019
@Georgelau-2019
Accidentally bump into spinalHDL. love it!
saahm
@saahm
        val inSamples = History(that = io.gpio, when=cfg_debounce_ena, length = 16)

I'm building a simple GPIO and wanted to add debounce via fabric controlled by two registers: enable the debounce, number of samples to take for debounce
Now what i understood is i can use History() to generate the sequence of samples from my input. That is returning a Vec of samples the size of my input per element and length of my History() parameter.
In order to implement the number of samples used for the MajorityVote I thought I would do

val sampledVal = MajorityVote(inSamples(0 to cfg_debounce_samples.asUInt))

But obviously I would need an Int not UInt. Would it still be possible to have the size of MajorityVote to be configurable?

Dolu1990
@Dolu1990
Ho, actualy you can't have that, basicaly, it is a similar issue than having a myBits(myUInt downto 0) which is a variable length at run time => KO
What you could do, would be to have static size, and than mux out / gate out a subset of it
Ncerzzk
@Ncerzzk

Hello, I have a regs list, and I want to implement the write and read port as the code below:

  val regsList = List(
    // number->reg
    9-> Counter,
    11->Compare,
    12->Status,
    13->Cause,
    14->EPC,
    15->PRid,
    16->Config,
    default->Counter
  )

  Counter := (Counter.asUInt+1).asBits

  io.readData := 0
  when(io.writeEn){
    io.addr.muxList(regsList) := io.writeData
  }otherwise{
    io.readData := io.addr.muxList(regsList)
  }

But the write code io.addr.muxList(regsList) := io.writeData doesn't work.
Is it means that I nead to write an ugly for-loop with when to realize this? Is there a simple way?

saahm
@saahm
@Dolu1990 thats what I thought. I already set the History to a fixed length already, so its just extracting the "window" of samples i want into MajorityVote then
Dolu1990
@Dolu1990

@Ncerzzk

But the write code io.addr.muxList(regsList) := io.writeData doesn't work.

What error it give ?

@saahm Hoo sorry, right. hmmm You might sadly have tow choices :
  • Instanciating one majorityVote for each of the length you want, and muxing out the result
  • Implementing a new version of MajorityVote which would support the configurable window size at runtime, i think it should be a separated version of MajorityVote, as the implementation can be different (using adders instead of pure logics)
saahm
@saahm
I will see how big it becomes with multiple MajorityVote calls, if it isnt too big its fine
Thanks!
Dolu1990
@Dolu1990
How many element max for the MajorityVote ?
saahm
@saahm
The Vector I get from History is like 16 samples I think.
Dolu1990
@Dolu1990
So, as the majority vote should always be used on odd number of inputs, you can maybe just force pairs of inputs value to 0 and 1 to balance it
saahm
@saahm
Odd number of samples, good point, i should make this a thing too
Maybe there is something overseen by me by not fully explaining what i do. The goal i try to achieve is: I'm building a GPIO and want to debouince the inputs. I have my module to have the inputs of the GPIO (8 of them in a vector) and i sample the vector with history (so i get a vector of vectors). Is calling majority vote preserve each input line seperately? (So its not collapsing all bits to a single one?)
Dolu1990
@Dolu1990
Hoo
Debouncing from mechanical switches ?
saahm
@saahm
yea thats what i thought to do with my gpio for some tests
debouncing is only needed when i use them as inputs for mechanical switches so i wanted to have a register that can enable and configure them
Dolu1990
@Dolu1990
So, i would say, the best way to debounce such things, is just to sample the input value at a slow period