by

Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Repo info
Activity
  • 08:22

    Dolu1990 on dev

    SigmaDelta now encode bitstream… (compare)

  • Sep 19 01:53
    wswslzp closed #346
  • Sep 19 01:53
    wswslzp commented #346
  • Sep 18 15:18
    Dolu1990 commented #346
  • Sep 18 14:08
    wswslzp opened #346
  • Sep 18 08:51
    Dolu1990 commented #345
  • Sep 18 08:47
    Dolu1990 closed #345
  • Sep 18 08:47

    Dolu1990 on dev

    fix #345 SimConfig.addIncludeDi… (compare)

  • Sep 18 03:42
    willchenyx opened #345
  • Sep 17 20:23

    Dolu1990 on dev

    fix deltasigma (compare)

  • Sep 17 20:13

    Dolu1990 on dev

    Fix deltasigma idle (compare)

  • Sep 17 20:04

    Dolu1990 on dev

    Fix DmaSg memory core priority … (compare)

  • Sep 17 18:44

    Dolu1990 on dev

    ClockDomain now has withAsyncRe… (compare)

  • Sep 17 09:30

    Dolu1990 on dev

    oneFilePerComponent EnumDefine … Merge pull request #344 from ji… (compare)

  • Sep 17 09:30
    Dolu1990 closed #344
  • Sep 17 09:29
    Dolu1990 commented #344
  • Sep 17 03:07
    jijingg edited #344
  • Sep 17 03:06
    jijingg opened #344
  • Sep 16 15:59

    Dolu1990 on dev

    sigmaDelta is now mono/stereo c… (compare)

  • Sep 16 09:27

    Dolu1990 on dev

    improve DmaSg DacSigmaDelta is now signed (compare)

bellaz89
@bellaz89
@jijingg Cool thanks :D , I will spread it as much as I can
MM
bellaz89
@bellaz89
I still get Could not find a kernel matching Scala. Please select a kernel:
is it normal?
Dolu1990
@Dolu1990
@jijingg i juste tried from my phone ( in travel ), but it seem that jupyter can’t get a scala kernel (on the binder)
Did i missed something ? Never used jupyter XD
Hoo forget about it, i were in the preview ^^
Winston Lowe
@wel97459
@jijingg that's cool
bellaz89
@bellaz89
Ok, I was able to run it too. Cool!
Also you did quite a thing doing all the images
Oron Port
@soronpo
It's really cool that this actually works on my phone
jijingg
@jijingg
thanks all <3, for the reason of my bad english, there may be a lot of flaws there. please correct me. If someone can complete other chapters, I think people will love you , hah ^^
@Dolu1990 can it work now ? github seems to have crashed for half an hour just now
Dolu1990
@Dolu1990
It work ^^
Georgelau-2019
@Georgelau-2019
Accidentally bump into spinalHDL. love it!
saahm
@saahm
        val inSamples = History(that = io.gpio, when=cfg_debounce_ena, length = 16)

I'm building a simple GPIO and wanted to add debounce via fabric controlled by two registers: enable the debounce, number of samples to take for debounce
Now what i understood is i can use History() to generate the sequence of samples from my input. That is returning a Vec of samples the size of my input per element and length of my History() parameter.
In order to implement the number of samples used for the MajorityVote I thought I would do

val sampledVal = MajorityVote(inSamples(0 to cfg_debounce_samples.asUInt))

But obviously I would need an Int not UInt. Would it still be possible to have the size of MajorityVote to be configurable?

Dolu1990
@Dolu1990
Ho, actualy you can't have that, basicaly, it is a similar issue than having a myBits(myUInt downto 0) which is a variable length at run time => KO
What you could do, would be to have static size, and than mux out / gate out a subset of it
Ncerzzk
@Ncerzzk

Hello, I have a regs list, and I want to implement the write and read port as the code below:

  val regsList = List(
    // number->reg
    9-> Counter,
    11->Compare,
    12->Status,
    13->Cause,
    14->EPC,
    15->PRid,
    16->Config,
    default->Counter
  )

  Counter := (Counter.asUInt+1).asBits

  io.readData := 0
  when(io.writeEn){
    io.addr.muxList(regsList) := io.writeData
  }otherwise{
    io.readData := io.addr.muxList(regsList)
  }

But the write code io.addr.muxList(regsList) := io.writeData doesn't work.
Is it means that I nead to write an ugly for-loop with when to realize this? Is there a simple way?

saahm
@saahm
@Dolu1990 thats what I thought. I already set the History to a fixed length already, so its just extracting the "window" of samples i want into MajorityVote then
Dolu1990
@Dolu1990

@Ncerzzk

But the write code io.addr.muxList(regsList) := io.writeData doesn't work.

What error it give ?

@saahm Hoo sorry, right. hmmm You might sadly have tow choices :
  • Instanciating one majorityVote for each of the length you want, and muxing out the result
  • Implementing a new version of MajorityVote which would support the configurable window size at runtime, i think it should be a separated version of MajorityVote, as the implementation can be different (using adders instead of pure logics)
saahm
@saahm
I will see how big it becomes with multiple MajorityVote calls, if it isnt too big its fine
Thanks!
Dolu1990
@Dolu1990
How many element max for the MajorityVote ?
saahm
@saahm
The Vector I get from History is like 16 samples I think.
Dolu1990
@Dolu1990
So, as the majority vote should always be used on odd number of inputs, you can maybe just force pairs of inputs value to 0 and 1 to balance it
saahm
@saahm
Odd number of samples, good point, i should make this a thing too
Maybe there is something overseen by me by not fully explaining what i do. The goal i try to achieve is: I'm building a GPIO and want to debouince the inputs. I have my module to have the inputs of the GPIO (8 of them in a vector) and i sample the vector with history (so i get a vector of vectors). Is calling majority vote preserve each input line seperately? (So its not collapsing all bits to a single one?)
Dolu1990
@Dolu1990
Hoo
Debouncing from mechanical switches ?
saahm
@saahm
yea thats what i thought to do with my gpio for some tests
debouncing is only needed when i use them as inputs for mechanical switches so i wanted to have a register that can enable and configure them
Dolu1990
@Dolu1990
So, i would say, the best way to debounce such things, is just to sample the input value at a slow period
ex each 10 ms
with majority vote you should anyway get sample at a slow rate for such switches, i'm not sure it is realy usefull (vs a simple slow 10 ms sampler)
Ncerzzk
@Ncerzzk

@Dolu1990 It can be compiled successfully, but the verilog code generated is not what I want.
For example, here is only a mux for read, and not something about writing data to the regs.

  ...
  reg        [31:0]   _zz_1_;
  always @ (*) begin
    io_readData = 32'h0;
    if(! io_writeEn) begin
      io_readData = _zz_1_;
    end
  end


  always @ (*) begin
    case(io_addr)
      6'b001001 : begin
        _zz_1_ = Counter;
      end
      6'b001011 : begin
        _zz_1_ = Compare;
      end
      ...
      default : begin
        _zz_1_ = Counter;
      end
    endcase
  end

  always @ (posedge clk) begin
    if(reset) begin
      Counter <= 32'h0;
    end else begin
      Counter <= _zz_2_;
    end
  end

So I suppose the problem may be in io.addr.muxList(regsList) := io.writeData
The return value of muxList seems not to be the old data of the regsList, but a new clone of it?

Dolu1990
@Dolu1990
Ahhh right
muxList is only to read a value, not to write it
I see your issue
Yes, sorry, you currently need a for loop
Ncerzzk
@Ncerzzk
OK, thanks. I just want to find a more simple way if possible .Ahhh
bellaz89
@bellaz89
@Ncerzzk Maybe it is not what you want.. but you could use a Mem (you lose your register naming though)
and it is less flexible..
Ncerzzk
@Ncerzzk
Yeah,thanks. It can work in Mem. May be I could get the reg name in other place.
Dolu1990
@Dolu1990
@jijingg
About drop/dropHigh what's about dropLow/dropHigh ?
agentdavo
@agentdavo_twitter
@jijingg comprehensive BMB chapter would be awesome! :-)
Dolu1990
@Dolu1990
about BMB i did some rework into its' parametrization to have per source ID parameters, to allow properly track features usages
Winston Lowe
@wel97459
In the FSM is there a way to have WhenIsNext run once, I would think that WhenIsActive that the code in the WhenIsNext should not continue to have an effect.
        val PaletteGetAndStore: State = new State {
            whenIsNext {
                when(!StateInit) {
                    ptr1 := 0x2100
                    ptr2 := 0x2101
                    ptr3 := 0x3fff
                }
            }

            whenIsActive {
                StateInit:= True
                ptr1 := ptr1 + 2
                ptr2 := ptr2 + 2
                ptr3 := ptr3 + 1
                when(ptr3 =/= 0x3fff){
                    Palettes(ptr3.resize(4)) := Data16.asUInt
                }
                when(ptr3 === 15) {
                    StateInit:= False
                    goto(SpriteInit)
                }
            }
        }