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  • Oct 18 10:20

    Dolu1990 on dev

    Add propagateIo USB OHCI host WIP (compare)

  • Oct 15 11:25

    Dolu1990 on v1.4.2

    (compare)

  • Oct 15 10:19

    Dolu1990 on dev

    version++ (compare)

  • Oct 15 08:59
    Dolu1990 commented #319
  • Oct 15 02:32
    wswslzp commented #319
  • Oct 13 12:37

    Dolu1990 on dev

    Improve StateMachine start/stop… Sync USB OHCI host WIP (compare)

  • Oct 13 07:58

    Dolu1990 on dev

    refractoring (compare)

  • Oct 05 15:01

    Dolu1990 on dev

    Fix Axi4WriteUpizeer and Axi4 w… (compare)

  • Oct 05 02:01
    japm48 edited #265
  • Oct 02 17:42

    Dolu1990 on dev

    Add SpiXdr.lazySclk (compare)

  • Oct 02 14:46

    Dolu1990 on dev

    mill dependency way added sbt compilePlugin dependency ad… Merge pull request #351 from ji… (compare)

  • Oct 02 14:46
    Dolu1990 closed #351
  • Oct 02 14:46
    Dolu1990 commented #351
  • Oct 02 14:13
    jijingg opened #351
  • Oct 01 09:31
    Dolu1990 commented #350
  • Oct 01 09:31

    Dolu1990 on dev

    VGA enable positive sync pulse VgaCtrl move polarity regs to t… VgaCtrl set default polarity to… and 1 more (compare)

  • Oct 01 09:31
    Dolu1990 closed #350
  • Oct 01 09:31
    Dolu1990 commented #348
  • Oct 01 09:31

    Dolu1990 on dev

    Fix UFix maxValue bug from issu… Merge pull request #348 from ph… (compare)

  • Oct 01 09:31
    Dolu1990 closed #348
Dolu1990
@Dolu1990
Debouncing from mechanical switches ?
saahm
@saahm
yea thats what i thought to do with my gpio for some tests
debouncing is only needed when i use them as inputs for mechanical switches so i wanted to have a register that can enable and configure them
Dolu1990
@Dolu1990
So, i would say, the best way to debounce such things, is just to sample the input value at a slow period
ex each 10 ms
with majority vote you should anyway get sample at a slow rate for such switches, i'm not sure it is realy usefull (vs a simple slow 10 ms sampler)
Ncerzzk
@Ncerzzk

@Dolu1990 It can be compiled successfully, but the verilog code generated is not what I want.
For example, here is only a mux for read, and not something about writing data to the regs.

  ...
  reg        [31:0]   _zz_1_;
  always @ (*) begin
    io_readData = 32'h0;
    if(! io_writeEn) begin
      io_readData = _zz_1_;
    end
  end


  always @ (*) begin
    case(io_addr)
      6'b001001 : begin
        _zz_1_ = Counter;
      end
      6'b001011 : begin
        _zz_1_ = Compare;
      end
      ...
      default : begin
        _zz_1_ = Counter;
      end
    endcase
  end

  always @ (posedge clk) begin
    if(reset) begin
      Counter <= 32'h0;
    end else begin
      Counter <= _zz_2_;
    end
  end

So I suppose the problem may be in io.addr.muxList(regsList) := io.writeData
The return value of muxList seems not to be the old data of the regsList, but a new clone of it?

Dolu1990
@Dolu1990
Ahhh right
muxList is only to read a value, not to write it
I see your issue
Yes, sorry, you currently need a for loop
Ncerzzk
@Ncerzzk
OK, thanks. I just want to find a more simple way if possible .Ahhh
bellaz89
@bellaz89
@Ncerzzk Maybe it is not what you want.. but you could use a Mem (you lose your register naming though)
and it is less flexible..
Ncerzzk
@Ncerzzk
Yeah,thanks. It can work in Mem. May be I could get the reg name in other place.
Dolu1990
@Dolu1990
@jijingg
About drop/dropHigh what's about dropLow/dropHigh ?
agentdavo
@agentdavo_twitter
@jijingg comprehensive BMB chapter would be awesome! :-)
Dolu1990
@Dolu1990
about BMB i did some rework into its' parametrization to have per source ID parameters, to allow properly track features usages
Winston Lowe
@wel97459
In the FSM is there a way to have WhenIsNext run once, I would think that WhenIsActive that the code in the WhenIsNext should not continue to have an effect.
        val PaletteGetAndStore: State = new State {
            whenIsNext {
                when(!StateInit) {
                    ptr1 := 0x2100
                    ptr2 := 0x2101
                    ptr3 := 0x3fff
                }
            }

            whenIsActive {
                StateInit:= True
                ptr1 := ptr1 + 2
                ptr2 := ptr2 + 2
                ptr3 := ptr3 + 1
                when(ptr3 =/= 0x3fff){
                    Palettes(ptr3.resize(4)) := Data16.asUInt
                }
                when(ptr3 === 15) {
                    StateInit:= False
                    goto(SpriteInit)
                }
            }
        }
this works.
jijingg
@jijingg

@Dolu1990 i did drop/dropHigh follow the habit of Scala drop/dropRight, and take/takeHigh also have the same situation, but dropLow/takeLow may be more intuitive , so there have two solution

  • replace drop/take bydropLow/takeLow
  • add dropLow/takeLow and keep drop/take for short

which you prefer?

jijingg
@jijingg
@agentdavo_twitter I haven't used BMB yet ,But I think it should be similar to AMBA. If necessary, consider adding it later
Dolu1990
@Dolu1990
@wel97459 Hmm, what's about using onEntry ?
Winston Lowe
@wel97459
i'll try that thanks @Dolu1990
Dolu1990
@Dolu1990
@jijingg For me, add dropLow/takeLow and keep drop/take for short is fine
Also, it keep backward compatibility
jijingg
@jijingg
ok
Winston Lowe
@wel97459
I'm working on a tilemap and sprite engine that will draw to an LCD
Dolu1990
@Dolu1990
About Bmb, it is kind of a middle ground between AXI4 and Avalon, which support invalidation based coherency
Winston Lowe
@wel97459
Picture of a Tile and Sprite engine I'm working on. And testing it out with ventilator and SDL2.
image.png
Winston Lowe
@wel97459
image.png
Winston Lowe
@wel97459
10 Sprites on a scan line, and a max of 40 total in a frame
bellaz89
@bellaz89
Very cool!
chwise
@chwise
do we have some examples/demos with a little complex reference model based on SpinalSim?
chwise
@chwise
I mean that input data of dut are different with the output(maybe trimmed some input data), not like fifo. That needs a reference model for verification.
Dolu1990
@Dolu1990
@chwise here you can find all the regression tests of SpinalHDL itself, the ones in SpinalSim contain SpinalSim in the file name :
https://github.com/SpinalHDL/SpinalHDL/tree/dev/tester/src/test/scala/spinal/tester/scalatest
Which is based on BmbBridgeTester
which basicly check byte access of a Bmb bridge
chwise
@chwise
Thank you for your share ^^
Dolu1990
@Dolu1990
I think there is a missing access primitive in SpinalSim, (to the already exisiting Int, Long, BigInt) which is to access things as byte array
jijingg
@jijingg
@Dolu1990 I dont catch the meaning, which primitive? dose the toBoolean,toInt, toLong, toBigInt are not enough?
Dolu1990
@Dolu1990
Right, none of them are good for raw data (many bytes)
BigInt is workable, but i'm not sure about the overhead
bellaz89
@bellaz89
+1 for toBytes (or toByteArray)
saahm
@saahm
So basically a List of Int/BigInt;
As soon as you can have an Array of Bytes, you'd maybe want an Array of Words too (thinking about the data that goes around on busses)
What kind of overhead is expected with BigInt?
I'm for toBytes/toByteArray aswell (at least when coming form classical HDL) since thinking in Int/Long/BigInt isnt natrual as compared to Bytes/Vector of Bytes
Dolu1990
@Dolu1990

as soon as you can have an array of bytes, you'd want an array of words maybe too

Right XD

Issue with big int is that there is no proper way to access its byte, or maybe i missed it.