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  • 12:06
    hanm2019 synchronize #1015
  • Jan 26 16:01
    jjyy-Huang synchronize #1010
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    jjyy-Huang synchronize #1010
  • Jan 26 14:51
    likewise commented #1028
  • Jan 26 14:42
    likewise opened #1028
  • Jan 26 14:14
    hanm2019 commented #1014
  • Jan 26 13:30
    Dolu1990 commented #1027
  • Jan 26 13:28
    Dolu1990 commented #1014
  • Jan 26 10:57

    Dolu1990 on naxriscv

    Add StreamDriverOoo (compare)

  • Jan 25 02:24
    hanm2019 edited #1015
  • Jan 24 12:14

    Dolu1990 on naxriscv

    Add AddressMapping.randomPick Fix SparseMemory array accesses (compare)

  • Jan 24 09:49
    hanm2019 commented #1015
  • Jan 24 05:36
    hanm2019 synchronize #1015
  • Jan 22 17:18
    pavel-demin commented #1011
  • Jan 22 15:20
    likewise commented #1011
  • Jan 22 15:19
    likewise commented #1011
  • Jan 22 14:29
    pavel-demin commented #1011
  • Jan 22 14:29
    pavel-demin commented #1011
  • Jan 22 13:49
    likewise commented #1011
  • Jan 22 13:20
    pavel-demin commented #1011
Dolu1990
@Dolu1990
withoutReset is a function callable on ClockDomain, to create a new clockdomain with the same properties but without reset capabilities
(new clock domain returned by withoutReset
Readon
@Readon
ahh
that's reasonable
understandable
Dolu1990
@Dolu1990
depend the perspective, i can understand it look weird XD
About the withPast, what's about pastSampled ?
hmm or pastValid ?
Readon
@Readon
pastValid shows that past is usable, i vote for it.^^
Dolu1990
@Dolu1990
I'm ok with it
Alexis Marquet
@allexoll
me too
saahm
@saahm
@Dolu1990 thanks again for the memory banking idea. That seems to work on my design, i now just have to fight that weird compressed instructions isa specification
Dolu1990
@Dolu1990
<3
korbin
@korbin
def streamReadSyncRegistered[T2 <: Data](cmd: Stream[UInt], linkedData: T2, crossClock:Boolean = false) : Stream[ReadRetLinked[T,T2]] = {
    val ret = Stream(new ReadRetLinked(mem.wordType, linkedData))

    val retData = mem.readSync(cmd.payload, cmd.ready, clockCrossing = crossClock)
    val retLinked = RegNextWhen(linkedData, cmd.ready)

    cmd.ready := ret.ready

    ret.valid := RegNext(RegNext(cmd.valid))
    ret.value := RegNext(retData)
    ret.linked := RegNext(retLinked)
    ret
  }

i cannot for the life of me figure out how to remove the bubble from this extension to Mem.scala.

BRAM requires an additional register stage to be absorbed for better timing in Xilinx devices, so RegNext(retData) should work, but then the handshake logic breaks

Dolu1990
@Dolu1990
Ahh you want to have it with the bram output register enabled ?
korbin
@korbin
yes
exactly
Dolu1990
@Dolu1990
Do you have a clock enable on that output register in the FPGA ?
korbin
@korbin
i am not sure if they allow clock enables or not - i believe so
it may be different for block ram / ultraram
Dolu1990
@Dolu1990
If yes, i would say, just use the regular streamReadSync, and add a returnStream.stage()
korbin
@korbin
i was doing that, they don't get absorbed
Dolu1990
@Dolu1990
XD
damned
korbin
@korbin
in that case, i do not think clock enables are allowed
Dolu1990
@Dolu1990
Sadness of my life
hmm
what's about using a low latency fifo on the output ? with "almostfull" style logic to halt the cmd stream ?
korbin
@korbin
there are a number of places where there is register absorbing in xilinx FPGAs like this - BRAM, URAM, DSP, etc
the verilog needs to look like:
always@(posedge clk) begin
       ram_out <= ram[addra];
       dout <= ram_out;
end
it feels like there should be a way to skid buffer this somehow but i am just not familiar enough yet with Stream
Dolu1990
@Dolu1990
val haltIt = Bool()
val cmdHalted = cmd.haltWhen(haltIt)
val rsp = mem.streamReadSync(cmdHalted).queueLowLatency(size=2)
haltIt := rsp.isStall()
Something in that kind ?
(but not exactly)
More like :
val haltIt = Bool()
val cmdHalted = cmd.haltWhen(haltIt).toFlow
val rsp = mem.flowReadSync(cmdHalted).toStream.queueLowLatency(size=2)
haltIt := rsp.isStall()
(flowReadSync isn't a thing in the lib)
korbin
@korbin
yeah this makes sense, thanks
Dolu1990
@Dolu1990
Ahhh missing one thing
mem.flowReadSync(cmdHalted).stage.toStream.
sebastien-riou
@sebastien-riou
question to scala gurus:
we have elegant way to concatenate "reads": myBits_24bits := bits_8bits_1 ## bits_8bits_2 ## bits_8bits_3
do we have an elegant way to concatenate "writes" ?
I tried a ## b ## c = d but it does not seems to work, at least when a,b,c are registers
Dolu1990
@Dolu1990
(a, b, c) := d should work
@sebastien-riou
as long as d is Bits
saahm
@saahm
will that translate to the verilog equivalent? like {a,b,c} = sameVal[idx] where sameVal[idx] is same width as a, b and c together?
Dolu1990
@Dolu1990
yes, but with one assigment per destination
saahm
@saahm
I dont know if thats 'wanted' behavior, but components with the same name in different packages cause the same simWorkspace subdirectory to be used, is that wanted behavior?
Dolu1990
@Dolu1990
in SpinalSim or SpinalFormal ?
saahm
@saahm
SpinalSim
I only had it happen once and I didnt try reproducing it yet tho
Dolu1990
@Dolu1990
It isn't wanted behaviour