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  • Nov 28 21:28
    kleinai commented #978
  • Nov 28 21:25
    numero-744 commented #968
  • Nov 28 21:19
    andreasWallner commented #978
  • Nov 28 21:01
    numero-744 synchronize #968
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    numero-744 synchronize #968
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  • Nov 28 18:15

    numero-744 on dev

    Deprecate Bool without braces move Bool to BoolFactory remove use of deprecated Bool and 1 more (compare)

korbin
@korbin
yes
exactly
Dolu1990
@Dolu1990
Do you have a clock enable on that output register in the FPGA ?
korbin
@korbin
i am not sure if they allow clock enables or not - i believe so
it may be different for block ram / ultraram
Dolu1990
@Dolu1990
If yes, i would say, just use the regular streamReadSync, and add a returnStream.stage()
korbin
@korbin
i was doing that, they don't get absorbed
Dolu1990
@Dolu1990
XD
damned
korbin
@korbin
in that case, i do not think clock enables are allowed
Dolu1990
@Dolu1990
Sadness of my life
hmm
what's about using a low latency fifo on the output ? with "almostfull" style logic to halt the cmd stream ?
korbin
@korbin
there are a number of places where there is register absorbing in xilinx FPGAs like this - BRAM, URAM, DSP, etc
the verilog needs to look like:
always@(posedge clk) begin
       ram_out <= ram[addra];
       dout <= ram_out;
end
it feels like there should be a way to skid buffer this somehow but i am just not familiar enough yet with Stream
Dolu1990
@Dolu1990
val haltIt = Bool()
val cmdHalted = cmd.haltWhen(haltIt)
val rsp = mem.streamReadSync(cmdHalted).queueLowLatency(size=2)
haltIt := rsp.isStall()
Something in that kind ?
(but not exactly)
More like :
val haltIt = Bool()
val cmdHalted = cmd.haltWhen(haltIt).toFlow
val rsp = mem.flowReadSync(cmdHalted).toStream.queueLowLatency(size=2)
haltIt := rsp.isStall()
(flowReadSync isn't a thing in the lib)
korbin
@korbin
yeah this makes sense, thanks
Dolu1990
@Dolu1990
Ahhh missing one thing
mem.flowReadSync(cmdHalted).stage.toStream.
sebastien-riou
@sebastien-riou
question to scala gurus:
we have elegant way to concatenate "reads": myBits_24bits := bits_8bits_1 ## bits_8bits_2 ## bits_8bits_3
do we have an elegant way to concatenate "writes" ?
I tried a ## b ## c = d but it does not seems to work, at least when a,b,c are registers
Dolu1990
@Dolu1990
(a, b, c) := d should work
@sebastien-riou
as long as d is Bits
saahm
@saahm
will that translate to the verilog equivalent? like {a,b,c} = sameVal[idx] where sameVal[idx] is same width as a, b and c together?
Dolu1990
@Dolu1990
yes, but with one assigment per destination
saahm
@saahm
I dont know if thats 'wanted' behavior, but components with the same name in different packages cause the same simWorkspace subdirectory to be used, is that wanted behavior?
Dolu1990
@Dolu1990
in SpinalSim or SpinalFormal ?
saahm
@saahm
SpinalSim
I only had it happen once and I didnt try reproducing it yet tho
Dolu1990
@Dolu1990
It isn't wanted behaviour
From a single run ?
or between multiple run ?
saahm
@saahm

So I have like

main/
|--foo
|    |--fooComp.scala
|    |--fooSim.scala
|
|--bar
     |--fooComp.scala
     |--fooSim.scala

in the the comp and sims are in different packages (also with the package statement at the head of the file). when I run the bar/fooSim it creates simWorkspace/fooComp, after that I run foo/fooSim and it overwrites the simWorkspace/fooComp from what I saw

Dolu1990
@Dolu1990
Ahh
yes it is expected
It would avoid the override if you were running them both in the same runtime
saahm
@saahm
like locking the directory?
Dolu1990
@Dolu1990
Yes
saahm
@saahm
ah ok
Dolu1990
@Dolu1990
and second one to come will be served with xxxx_1 as workspace
saahm
@saahm
when they are executed at the same time
Dolu1990
@Dolu1990
yes
saahm
@saahm
quite an "undocumented" feature xD
Dolu1990
@Dolu1990
XD
saahm
@saahm
wouldnt it be useful to have same-name components from different packages use different simulation-results-directory?