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  • 14:31

    Dolu1990 on dev

    getAheadValue now allows overri… (compare)

  • 12:11

    Dolu1990 on dev

    Fix typo (compare)

  • 11:47

    Dolu1990 on dev

    Add Nameable.setLandaName allow… (compare)

  • 01:37
    Readon commented #968
  • 01:22
    Readon closed #978
  • 01:22

    Readon on dev

    Fix SimBigIntPimper toBytes Fi… Merge pull request #979 from an… (compare)

  • 01:22
    Readon closed #979
  • Dec 04 19:49
    numero-744 commented #982
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    Readon commented #982
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    Readon commented #982
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    Readon commented #982
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    numero-744 commented #982
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    Readon commented #982
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    Readon commented #982
Dolu1990
@Dolu1990
damned
korbin
@korbin
in that case, i do not think clock enables are allowed
Dolu1990
@Dolu1990
Sadness of my life
hmm
what's about using a low latency fifo on the output ? with "almostfull" style logic to halt the cmd stream ?
korbin
@korbin
there are a number of places where there is register absorbing in xilinx FPGAs like this - BRAM, URAM, DSP, etc
the verilog needs to look like:
always@(posedge clk) begin
       ram_out <= ram[addra];
       dout <= ram_out;
end
it feels like there should be a way to skid buffer this somehow but i am just not familiar enough yet with Stream
Dolu1990
@Dolu1990
val haltIt = Bool()
val cmdHalted = cmd.haltWhen(haltIt)
val rsp = mem.streamReadSync(cmdHalted).queueLowLatency(size=2)
haltIt := rsp.isStall()
Something in that kind ?
(but not exactly)
More like :
val haltIt = Bool()
val cmdHalted = cmd.haltWhen(haltIt).toFlow
val rsp = mem.flowReadSync(cmdHalted).toStream.queueLowLatency(size=2)
haltIt := rsp.isStall()
(flowReadSync isn't a thing in the lib)
korbin
@korbin
yeah this makes sense, thanks
Dolu1990
@Dolu1990
Ahhh missing one thing
mem.flowReadSync(cmdHalted).stage.toStream.
sebastien-riou
@sebastien-riou
question to scala gurus:
we have elegant way to concatenate "reads": myBits_24bits := bits_8bits_1 ## bits_8bits_2 ## bits_8bits_3
do we have an elegant way to concatenate "writes" ?
I tried a ## b ## c = d but it does not seems to work, at least when a,b,c are registers
Dolu1990
@Dolu1990
(a, b, c) := d should work
@sebastien-riou
as long as d is Bits
saahm
@saahm
will that translate to the verilog equivalent? like {a,b,c} = sameVal[idx] where sameVal[idx] is same width as a, b and c together?
Dolu1990
@Dolu1990
yes, but with one assigment per destination
saahm
@saahm
I dont know if thats 'wanted' behavior, but components with the same name in different packages cause the same simWorkspace subdirectory to be used, is that wanted behavior?
Dolu1990
@Dolu1990
in SpinalSim or SpinalFormal ?
saahm
@saahm
SpinalSim
I only had it happen once and I didnt try reproducing it yet tho
Dolu1990
@Dolu1990
It isn't wanted behaviour
From a single run ?
or between multiple run ?
saahm
@saahm

So I have like

main/
|--foo
|    |--fooComp.scala
|    |--fooSim.scala
|
|--bar
     |--fooComp.scala
     |--fooSim.scala

in the the comp and sims are in different packages (also with the package statement at the head of the file). when I run the bar/fooSim it creates simWorkspace/fooComp, after that I run foo/fooSim and it overwrites the simWorkspace/fooComp from what I saw

Dolu1990
@Dolu1990
Ahh
yes it is expected
It would avoid the override if you were running them both in the same runtime
saahm
@saahm
like locking the directory?
Dolu1990
@Dolu1990
Yes
saahm
@saahm
ah ok
Dolu1990
@Dolu1990
and second one to come will be served with xxxx_1 as workspace
saahm
@saahm
when they are executed at the same time
Dolu1990
@Dolu1990
yes
saahm
@saahm
quite an "undocumented" feature xD
Dolu1990
@Dolu1990
XD
saahm
@saahm
wouldnt it be useful to have same-name components from different packages use different simulation-results-directory?
i was quite confused when i saw it landed in the same directory and overwrote the old results of the other package
(not that this would be any important at the moment anyway)
(if i'd want to compare i'd copy the directory anyway)
Dolu1990
@Dolu1990
so, i was considering that conflicts would be unlikely / corner cases
It could be usefull yes
But then you may have to dig into hearchy of folder which would map the package structure
Not necessarly so much better (balance)
saahm
@saahm
yea, and in the end i think it should rarely happen that you will have the same component name across two or more packages where you start comparing simulations.
Naming components is such a time intense task you'd not name two components the same if they arent the same and should be a unique component anyway.