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  • Oct 06 19:24
    BracketMaster commented #202
  • Oct 06 15:05
    01xz commented #886
  • Oct 06 14:56
    Readon commented #886
  • Oct 06 14:40
    01xz closed #886
  • Oct 06 14:40
    01xz commented #886
  • Oct 06 14:25
    Dolu1990 commented #886
  • Oct 06 13:45
    01xz opened #886
  • Oct 06 13:44
    Readon closed #872
  • Oct 06 10:26
    Dolu1990 commented #885
  • Oct 06 10:25
    Dolu1990 commented #885
  • Oct 06 10:25
    Dolu1990 closed #885
  • Oct 06 10:25

    Dolu1990 on dev

    Fix #885 Toplevel names are now… (compare)

  • Oct 06 10:09
    Dolu1990 commented #843
  • Oct 06 09:51
    Dolu1990 commented #884
  • Oct 06 09:50
    Dolu1990 commented #879
  • Oct 06 09:50
    Dolu1990 commented #879
  • Oct 06 09:47
    Dolu1990 commented #879
  • Oct 06 04:29
    balanx opened #885
  • Oct 05 22:13
    kleinai commented #843
  • Oct 05 22:12
    kleinai synchronize #843
Dolu1990
@Dolu1990
(flowReadSync isn't a thing in the lib)
korbin
@korbin
yeah this makes sense, thanks
Dolu1990
@Dolu1990
Ahhh missing one thing
mem.flowReadSync(cmdHalted).stage.toStream.
sebastien-riou
@sebastien-riou
question to scala gurus:
we have elegant way to concatenate "reads": myBits_24bits := bits_8bits_1 ## bits_8bits_2 ## bits_8bits_3
do we have an elegant way to concatenate "writes" ?
I tried a ## b ## c = d but it does not seems to work, at least when a,b,c are registers
Dolu1990
@Dolu1990
(a, b, c) := d should work
@sebastien-riou
as long as d is Bits
saahm
@saahm
will that translate to the verilog equivalent? like {a,b,c} = sameVal[idx] where sameVal[idx] is same width as a, b and c together?
Dolu1990
@Dolu1990
yes, but with one assigment per destination
saahm
@saahm
I dont know if thats 'wanted' behavior, but components with the same name in different packages cause the same simWorkspace subdirectory to be used, is that wanted behavior?
Dolu1990
@Dolu1990
in SpinalSim or SpinalFormal ?
saahm
@saahm
SpinalSim
I only had it happen once and I didnt try reproducing it yet tho
Dolu1990
@Dolu1990
It isn't wanted behaviour
From a single run ?
or between multiple run ?
saahm
@saahm

So I have like

main/
|--foo
|    |--fooComp.scala
|    |--fooSim.scala
|
|--bar
     |--fooComp.scala
     |--fooSim.scala

in the the comp and sims are in different packages (also with the package statement at the head of the file). when I run the bar/fooSim it creates simWorkspace/fooComp, after that I run foo/fooSim and it overwrites the simWorkspace/fooComp from what I saw

Dolu1990
@Dolu1990
Ahh
yes it is expected
It would avoid the override if you were running them both in the same runtime
saahm
@saahm
like locking the directory?
Dolu1990
@Dolu1990
Yes
saahm
@saahm
ah ok
Dolu1990
@Dolu1990
and second one to come will be served with xxxx_1 as workspace
saahm
@saahm
when they are executed at the same time
Dolu1990
@Dolu1990
yes
saahm
@saahm
quite an "undocumented" feature xD
Dolu1990
@Dolu1990
XD
saahm
@saahm
wouldnt it be useful to have same-name components from different packages use different simulation-results-directory?
i was quite confused when i saw it landed in the same directory and overwrote the old results of the other package
(not that this would be any important at the moment anyway)
(if i'd want to compare i'd copy the directory anyway)
Dolu1990
@Dolu1990
so, i was considering that conflicts would be unlikely / corner cases
It could be usefull yes
But then you may have to dig into hearchy of folder which would map the package structure
Not necessarly so much better (balance)
saahm
@saahm
yea, and in the end i think it should rarely happen that you will have the same component name across two or more packages where you start comparing simulations.
Naming components is such a time intense task you'd not name two components the same if they arent the same and should be a unique component anyway.
so was just a curiosity
Dolu1990
@Dolu1990
Worst case, i think there is a option to set the workspace folder
saahm
@saahm
oh, that makes it even less problematic
Mingo
@mingo99
How to avoid generating “data_addr_1"
image.png
image.png
Dolu1990
@Dolu1990
is there any other referenec to data_addr_1 in the generated verilog file ?
Mingo
@mingo99
no
Dolu1990
@Dolu1990
how many bits is data_addr ?
Mingo
@mingo99
image.png
saahm
@saahm
weird duplication hm
Mingo
@mingo99
yeah,it is so confusing