So I have like
main/
|--foo
| |--fooComp.scala
| |--fooSim.scala
|
|--bar
|--fooComp.scala
|--fooSim.scalain the the comp and sims are in different packages (also with the package statement at the head of the file). when I run the bar/fooSim it creates simWorkspace/fooComp, after that I run foo/fooSim and it overwrites the simWorkspace/fooComp from what I saw
yes it is expected
It would avoid the override if you were running them both in the same runtime
i was quite confused when i saw it landed in the same directory and overwrote the old results of the other package
(not that this would be any important at the moment anyway)
(if i'd want to compare i'd copy the directory anyway)
It could be usefull yes
But then you may have to dig into hearchy of folder which would map the package structure
Not necessarly so much better (balance)
yea, and in the end i think it should rarely happen that you will have the same component name across two or more packages where you start comparing simulations.
Naming components is such a time intense task you'd not name two components the same if they arent the same and should be a unique component anyway.
Naming components is such a time intense task you'd not name two components the same if they arent the same and should be a unique component anyway.
so was just a curiosity
I can't reproduce the case (at least in dev) :
val a = B(0, 8 bits)
val b = B(0, 8 bits)
val c = a ## b(2, 3 bits)
val sub = new Component {
val d = in Bits(11 bits)
}
sub.d := c wire [7:0] a;
wire [7:0] b;
wire [10:0] c;
unamed sub (
.d (c[10:0] ) //i
);
assign a = 8'h0;
assign b = 8'h0;
assign c = {a,b[4 : 2]};
Woudl need a self contained example to try it
@mingo99
It's wonderful that SpinalHDL simulation supports VCS now. But there is a question that confuses me. When I simulate an external IP (e.g. Xilinx FIFO) with the Blackbox, how should I add the pre-compiled library to link it? I couldn't find the API mentioned in the documentation. The mapping of synopsys_sim.setup is also not done by just passing the compile parameter via VCSFlags.
@jjyy-Huang Can you open a issue on https://github.com/SpinalHDL/SpinalHDL about it ?
I personnaly don't know much about that part of the flow, but others may be able to track the issue on github ^^
I personnaly don't know much about that part of the flow, but others may be able to track the issue on github ^^
@korbin What do you mean by without a bubble ?
1 cycle latency ? or having lower bandwidth ? myFifo.io.pop.stage() isn't good ?
