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  • 21:52
    kleinai synchronize #821
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    Readon synchronize #774
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    Readon synchronize #774
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    kleinai commented #821
  • 08:13
    Dolu1990 commented #821
  • 07:57
    Dolu1990 commented #817
  • 02:04
    kleinai opened #821
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  • Aug 12 09:51
    Dolu1990 commented #818
  • Aug 12 08:53
    Dolu1990 commented #820
  • Aug 12 01:25
    dokleina opened #820
  • Aug 11 16:56

    Dolu1990 on scala3-dev

    various fixes portable to scala… Comment out macroes (compare)

  • Aug 11 16:55

    Dolu1990 on scala3-dev

    scala3 comment out regif macro … (compare)

  • Aug 11 16:55

    Dolu1990 on scala3-dev

    Fix compiler plugin for classes… randBoot now accept both dotted… scala3 spinalEnumSelectable and 4 more (compare)

  • Aug 11 14:57
    dzx-dzx commented #816
Dolu1990
@Dolu1990
But then you may have to dig into hearchy of folder which would map the package structure
Not necessarly so much better (balance)
saahm
@saahm
yea, and in the end i think it should rarely happen that you will have the same component name across two or more packages where you start comparing simulations.
Naming components is such a time intense task you'd not name two components the same if they arent the same and should be a unique component anyway.
so was just a curiosity
Dolu1990
@Dolu1990
Worst case, i think there is a option to set the workspace folder
saahm
@saahm
oh, that makes it even less problematic
Mingo
@mingo99
How to avoid generating “data_addr_1"
image.png
image.png
Dolu1990
@Dolu1990
is there any other referenec to data_addr_1 in the generated verilog file ?
Mingo
@mingo99
no
Dolu1990
@Dolu1990
how many bits is data_addr ?
Mingo
@mingo99
image.png
saahm
@saahm
weird duplication hm
Mingo
@mingo99
yeah,it is so confusing
Dolu1990
@Dolu1990
I can't reproduce the case (at least in dev) :
    val a = B(0, 8 bits)
    val b = B(0, 8 bits)
    val c = a ## b(2, 3 bits)

    val sub = new Component {
      val d = in Bits(11 bits)
    }
    sub.d := c
  wire       [7:0]    a;
  wire       [7:0]    b;
  wire       [10:0]   c;

  unamed sub (
    .d    (c[10:0]  )  //i
  );
  assign a = 8'h0;
  assign b = 8'h0;
  assign c = {a,b[4 : 2]};
Woudl need a self contained example to try it
@mingo99
Mingo
@mingo99
Thanks,I'll try it
Readon
@Readon
I suppose it is all about the data_addr is used as address of memory.
Mingo
@mingo99
Yeah, would you have a solution?
Readon
@Readon
no, it's just a suggestion^^
Jerry Huang
@jjyy-Huang
It's wonderful that SpinalHDL simulation supports VCS now. But there is a question that confuses me. When I simulate an external IP (e.g. Xilinx FIFO) with the Blackbox, how should I add the pre-compiled library to link it? I couldn't find the API mentioned in the documentation. The mapping of synopsys_sim.setup is also not done by just passing the compile parameter via VCSFlags.
korbin
@korbin
is it possible to register the StreamFifo pop valid value without a bubble?
saahm
@saahm
just RegNext?
Dolu1990
@Dolu1990
@jjyy-Huang Can you open a issue on https://github.com/SpinalHDL/SpinalHDL about it ?
I personnaly don't know much about that part of the flow, but others may be able to track the issue on github ^^
@korbin What do you mean by without a bubble ?
1 cycle latency ? or having lower bandwidth ? myFifo.io.pop.stage() isn't good ?
Pu Wang
@pwang7
After I upgraded to 1.7.0, the L"" interpolation of assert message seems not work, what's the new assert message interpolation?
Dolu1990
@Dolu1990

nterpolation of assert message seems not work

Which kind of issue is there ?
scala does not compile ? or Runtime crash or runtime not doing things right ?

saahm
@saahm
Is it possible to have FST instead of VCD for wavetraces? I havent found anything in the documentation yet
Kellen Wang
@kellenwang1017
is it possible to remove a clockdomain.setSyncWith effect?
A.M.
@allexoll

Is it possible to have FST instead of VCD for wavetraces? I havent found anything in the documentation yet

you can do it with withFstWave: https://github.com/SpinalHDL/SpinalHDL/blob/e40a9b01419fc01104e15d73b585c730c7c2fb6f/lib/src/main/scala/spinal/lib/fsm/Example.scala#L645

@saahm
saahm
@saahm
ah cool. nice
thanks!
Pu Wang
@pwang7
Screenshot from 2022-05-20 21-00-29.png
If the assert message is L"...", then compiler error: Cannot resolve overloaded method 'assert'
A.M.
@allexoll
is string interpolation not with s”…”
println(s"Hello, $name") // Hello, James ?
A.M.
@allexoll
ah fair enough for hdl reports my bad
I don’t know then
Dolu1990
@Dolu1990
@pwang7 assert(False, L"miaou $False", FAILURE) is fine for me
Can you provide a full example ?
(in copy pastable code) ^^
You can use
```scala
your scala code here
```
Pu Wang
@pwang7

@pwang7 assert(False, L"miaou $False", FAILURE) is fine for me

I prepared a simple example to illustrate the compiler error of the L"" interpolate in assert:

https://github.com/pwang7/SpinalAssertDemo

after clone the repo, just run ./run.sh to compile and it shows the error:

./run.sh 
+ export MILL_VERSION=0.10.3
+ [ ! -f mill ]
+ MILL=./mill --no-server
+ ./mill --no-server version
[1/1] version 
0.10.3
+ mkdir -p ./rtl
+ ./mill --no-server _.runMain AssertDemo
[31/42] demo.compile 
[info] compiling 1 Scala source to /home/pwang/Downloads/code/SpinalAssertDemo/out/demo/compile.dest/classes ...
[error] /home/pwang/Downloads/code/SpinalAssertDemo/demo/src/demo.scala:12:3: overloaded method assert with alternatives:
[error]   (assertion: spinal.core.Bool,message: Seq[Any])(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error]   (assertion: spinal.core.Bool,message: String)(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error]   (assertion: spinal.core.Bool,severity: spinal.core.AssertNodeSeverity)(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error]   (assertion: Boolean,message: => Any)(implicit loc: spinal.idslplugin.Location): Unit
[error]  cannot be applied to (spinal.core.Bool, spinal.core.LiteralBuilder#LList)
[error]   assert(False, L"${REPORT_TIME} time: ${io.input.payload}")
[error]   ^
[error] one error found
1 targets failed
demo.compile Compilation failed
Kellen Wang
@kellenwang1017
how to send stimulus to TriState type of io in doSim?
Dongwei939
@Dongwei939
hello, if anyone can tell me how can i joint two signals? such as { } in verilog