I can't reproduce the case (at least in dev) :
val a = B(0, 8 bits)
val b = B(0, 8 bits)
val c = a ## b(2, 3 bits)
val sub = new Component {
val d = in Bits(11 bits)
}
sub.d := c wire [7:0] a;
wire [7:0] b;
wire [10:0] c;
unamed sub (
.d (c[10:0] ) //i
);
assign a = 8'h0;
assign b = 8'h0;
assign c = {a,b[4 : 2]};
Woudl need a self contained example to try it
@mingo99
It's wonderful that SpinalHDL simulation supports VCS now. But there is a question that confuses me. When I simulate an external IP (e.g. Xilinx FIFO) with the Blackbox, how should I add the pre-compiled library to link it? I couldn't find the API mentioned in the documentation. The mapping of synopsys_sim.setup is also not done by just passing the compile parameter via VCSFlags.
@jjyy-Huang Can you open a issue on https://github.com/SpinalHDL/SpinalHDL about it ?
I personnaly don't know much about that part of the flow, but others may be able to track the issue on github ^^
I personnaly don't know much about that part of the flow, but others may be able to track the issue on github ^^
@korbin What do you mean by without a bubble ?
1 cycle latency ? or having lower bandwidth ? myFifo.io.pop.stage() isn't good ?
Is it possible to have FST instead of VCD for wavetraces? I havent found anything in the documentation yet
you can do it with withFstWave: https://github.com/SpinalHDL/SpinalHDL/blob/e40a9b01419fc01104e15d73b585c730c7c2fb6f/lib/src/main/scala/spinal/lib/fsm/Example.scala#L645
@saahm
thanks!
If the assert message is L"...", then compiler error: Cannot resolve overloaded method 'assert'
println(s"Hello, $name") // Hello, James ?
SpinalHDL documentation mentions L for
report: https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Other%20language%20features/report.html?highlight=report
I don’t know then
Can you provide a full example ?
(in copy pastable code) ^^
You can use
```scala
your scala code here
```
```scala
your scala code here
```
@pwang7 assert(False, L"miaou $False", FAILURE) is fine for me
I prepared a simple example to illustrate the compiler error of the L"" interpolate in assert:
https://github.com/pwang7/SpinalAssertDemo
after clone the repo, just run ./run.sh to compile and it shows the error:
./run.sh
+ export MILL_VERSION=0.10.3
+ [ ! -f mill ]
+ MILL=./mill --no-server
+ ./mill --no-server version
[1/1] version
0.10.3
+ mkdir -p ./rtl
+ ./mill --no-server _.runMain AssertDemo
[31/42] demo.compile
[info] compiling 1 Scala source to /home/pwang/Downloads/code/SpinalAssertDemo/out/demo/compile.dest/classes ...
[error] /home/pwang/Downloads/code/SpinalAssertDemo/demo/src/demo.scala:12:3: overloaded method assert with alternatives:
[error] (assertion: spinal.core.Bool,message: Seq[Any])(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error] (assertion: spinal.core.Bool,message: String)(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error] (assertion: spinal.core.Bool,severity: spinal.core.AssertNodeSeverity)(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error] (assertion: Boolean,message: => Any)(implicit loc: spinal.idslplugin.Location): Unit
[error] cannot be applied to (spinal.core.Bool, spinal.core.LiteralBuilder#LList)
[error] assert(False, L"${REPORT_TIME} time: ${io.input.payload}")
[error] ^
[error] one error found
1 targets failed
demo.compile Compilation failed
can you tell me why?Please~
@allexoll Thanks ^^
class TopLevel extends Component {
val io = new Bundle {
val sink_data = in UInt(1 bit)
val sink_data_valid = in Bool()
val source_pam4 = out UInt(2 bits)
// val source_pam4_valid = out Bool()
}
val sink_data_r = Reg(UInt(2 bits))
sink_data_r := (io.sink_data , io.sink_data)type mismatch;
[error] found : spinal.core.UInt
[error] required: (Any, Any)
[error] sink_data_r := (io.sink_data , io.sink_data)
[error] ^
Should be considered as a experimental API
@Dongwei939 Ahhhh, sink_data_r := io.sink_data @@ io.sink_data