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  • 14:03
    Dolu1990 commented #788
  • 08:52
    dnltz commented #788
  • Jun 27 21:13
    kleinai commented #788
  • Jun 27 11:09
    kleinai commented #788
  • Jun 27 09:30
    dnltz commented #769
  • Jun 27 09:19
    dnltz edited #788
  • Jun 27 09:18
    dnltz edited #788
  • Jun 27 09:18
    dnltz synchronize #788
  • Jun 27 09:16
    dnltz opened #788
  • Jun 27 07:32
    Dolu1990 commented #785
  • Jun 27 07:31
    Dolu1990 commented #785
  • Jun 27 07:31
    Dolu1990 closed #785
  • Jun 27 07:31

    Dolu1990 on dev

    Fix #785 : When setInlineVerilo… (compare)

  • Jun 25 09:14

    Dolu1990 on dev

    Fix BmbToWishbone burst and bac… (compare)

  • Jun 25 08:48

    Dolu1990 on dev

    Fix symplify cache ? (compare)

  • Jun 24 09:37
    Dolu1990 commented #763
  • Jun 23 20:09
    jonnykl commented #763
  • Jun 23 14:43
    Dolu1990 commented #786
  • Jun 23 13:58
    Dolu1990 commented #784
  • Jun 23 01:34
    kellenwang1017 opened #786
saahm
@saahm
Is it possible to have FST instead of VCD for wavetraces? I havent found anything in the documentation yet
Kellen Wang
@kellenwang1017
is it possible to remove a clockdomain.setSyncWith effect?
A.M.
@allexoll

Is it possible to have FST instead of VCD for wavetraces? I havent found anything in the documentation yet

you can do it with withFstWave: https://github.com/SpinalHDL/SpinalHDL/blob/e40a9b01419fc01104e15d73b585c730c7c2fb6f/lib/src/main/scala/spinal/lib/fsm/Example.scala#L645

@saahm
saahm
@saahm
ah cool. nice
thanks!
Pu Wang
@pwang7
Screenshot from 2022-05-20 21-00-29.png
If the assert message is L"...", then compiler error: Cannot resolve overloaded method 'assert'
A.M.
@allexoll
is string interpolation not with s”…”
println(s"Hello, $name") // Hello, James ?
A.M.
@allexoll
ah fair enough for hdl reports my bad
I don’t know then
Dolu1990
@Dolu1990
@pwang7 assert(False, L"miaou $False", FAILURE) is fine for me
Can you provide a full example ?
(in copy pastable code) ^^
You can use
```scala
your scala code here
```
Pu Wang
@pwang7

@pwang7 assert(False, L"miaou $False", FAILURE) is fine for me

I prepared a simple example to illustrate the compiler error of the L"" interpolate in assert:

https://github.com/pwang7/SpinalAssertDemo

after clone the repo, just run ./run.sh to compile and it shows the error:

./run.sh 
+ export MILL_VERSION=0.10.3
+ [ ! -f mill ]
+ MILL=./mill --no-server
+ ./mill --no-server version
[1/1] version 
0.10.3
+ mkdir -p ./rtl
+ ./mill --no-server _.runMain AssertDemo
[31/42] demo.compile 
[info] compiling 1 Scala source to /home/pwang/Downloads/code/SpinalAssertDemo/out/demo/compile.dest/classes ...
[error] /home/pwang/Downloads/code/SpinalAssertDemo/demo/src/demo.scala:12:3: overloaded method assert with alternatives:
[error]   (assertion: spinal.core.Bool,message: Seq[Any])(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error]   (assertion: spinal.core.Bool,message: String)(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error]   (assertion: spinal.core.Bool,severity: spinal.core.AssertNodeSeverity)(implicit loc: spinal.idslplugin.Location): spinal.core.internals.AssertStatement <and>
[error]   (assertion: Boolean,message: => Any)(implicit loc: spinal.idslplugin.Location): Unit
[error]  cannot be applied to (spinal.core.Bool, spinal.core.LiteralBuilder#LList)
[error]   assert(False, L"${REPORT_TIME} time: ${io.input.payload}")
[error]   ^
[error] one error found
1 targets failed
demo.compile Compilation failed
Kellen Wang
@kellenwang1017
how to send stimulus to TriState type of io in doSim?
Dongwei939
@Dongwei939
hello, if anyone can tell me how can i joint two signals? such as { } in verilog
jijingg
@jijingg
e := (a,b,c,d)
Dongwei939
@Dongwei939
thank you!!
jijingg
@jijingg
(a,b,c,d) := e
Dongwei939
@Dongwei939
thank you!
Dongwei939
@Dongwei939
type mismatch;
[error] found : spinal.core.UInt
[error] required: (Any, Any)
[error] pam4_c_data := (io.sink_data,io.sink_data)
can you tell me why?Please~
A.M.
@allexoll
EstablishedHDLs-FCCM.pdf
Dolu1990
@Dolu1990
@Dongwei939 what are pam4_c_data and io.sink_data
@allexoll Thanks ^^
Dongwei939
@Dongwei939
class TopLevel extends Component {
val io = new Bundle {
val sink_data       = in UInt(1 bit)
val sink_data_valid = in Bool()

val source_pam4       = out UInt(2 bits)
// val source_pam4_valid = out Bool()
}
val sink_data_r   = Reg(UInt(2 bits))


sink_data_r := (io.sink_data , io.sink_data)
@Dolu1990 thanks ! this is my code.
type mismatch;
[error]  found   : spinal.core.UInt
[error]  required: (Any, Any)
[error] sink_data_r := (io.sink_data , io.sink_data)
[error]                    ^
Dolu1990
@Dolu1990
I moved the NaxRiscv pipeline tool into the spinal.lib.pipeline package (for all)
Should be considered as a experimental API
@Dongwei939 Ahhhh, sink_data_r := io.sink_data @@ io.sink_data
@@ is to concatenate 2 things and preserve the type (UInt/SInt)
## is for concatenate things in raw mode (always return Bits)
Côme
@come_744:tedomum.net
[m]
Without Markdown interpretation: and ## is for raw mode
Dongwei939
@Dongwei939
oh! thank you!!!
志哈
@zhiha
hello~Dolu, I want to know how to init a ram, without generating the initializing .bin file. My team is using the vivado to synthesis which does not support the "readmemb".
Dolu1990
@Dolu1990
@zhiha In the SpinalConfig, you can set inlineRom to true
@kervel wrong channel ^^ ?
志哈
@zhiha
@Dolu1990 thanks, I'll try ^^
Côme
@come_744:tedomum.net
[m]
Hello, a few days ago Scala started printing warnings with assignments in my test benches: reflective access of structural type member value start should be enabled
import dut.io

io.start #= true
It does not always print this message. What do you think about it?
Dolu1990
@Dolu1990
Hi, does it print it during the testbench runtime ? or before, during the elaboration of the hardware ?
Seems like at testbench runtime if i understand well
that's a weird one
Côme
@come_744:tedomum.net
[m]
It is printed at compile time
Dolu1990
@Dolu1990
I had it too just today
compile time ?