SpinalHDL/SpinalHDL

SpinalHDL core

Dolu1990

@Dolu1990

@saahm in SpinalSim ?

you will have to dump it yourself accessing word by word in a loop

saahm

@saahm

yea with "Mem.getBigInt(idx)" right?

PasCal++

@hlw:matrix.org

[m]

Hi, I'm developing a visual simulation tool for spinal: https://github.com/volatile-static/SpinalVS Any suggestions?

Dolu1990

@Dolu1990

@saahm Yes

@hlw:matrix.org Hmm can you save the inputs to reaply them to a futur session ?

2 replies

Kellen Wang

@kellenwang1017

how can i force a signal to a fixed value no matter what is assigned by other #= statement?

in simulation only of course

saahm

@saahm

on the testbench part?

you can drive it starting from the moment you initialize the clock, but theoretically you can put that driving into a seperate fork so that it gets driven all the time technically speaking

thats what i would try first

Kellen Wang

@kellenwang1017

that's also what pops up into my head when comes to this, but i think glitches are inevitable by applying such trick, wonder if there's other better way for sure

saahm

@saahm

as long as the assignment happen with the same clock edge stimulus only one should pass (and that should be the last). Technically thats fast to try out I'd guess

but usually, if you drive it once, and then it stays untouched it should keep its value fixed

Kellen Wang

@kellenwang1017

i tried such thing by mistaken before, so i know what's gonna happen

i used to have two fork block assigning to same io, which was just a mess

however some times we need a fixed priority for assignments

for example, we have a normal test case which works fine, then we wanna make a exceptional situation when something is wrong

the easiest way to do it is to force one of the signal to a fixed error state for a short period of time, such error state should be allowed to happen at many different phases of the test

Kellen Wang

@kellenwang1017

if i have to add such process to all phases of my sim io driver, that's gonna be killing me

yuqi-ali

@yuqi-ali

@Dolu1990 I get a error while simulating the ddr ip . the ddr ctrl ip have inout pins,and the memory modle has it too. I write blackbox each one, get a error while connect the two inout pin together:

asd
ERROR !
A null pointer access has been detected in the JVM.
This could happen when in your SpinalHDL description, you access an signal which is only defined further.
For instance :
  val result = Bool()
  result := a ^ b  //a and b can't be accessed there because they are only defined one line below (Software rule of execution order)
  val a,b = Bool()

Côme

@come_744:tedomum.net

[m]

You have to put val a, b = Bool() above result := a ^ b

So maybe it is that you have used ports of an entity before instanciating it (plz show some code for more accurate advice)

yuqi-ali

@yuqi-ali

I wil write a demo later. It's not the reason

case class A() extends BlackBox{
val data=inout(Analog(Bool()))
}
case class B() extends BlackBox{
val data=inout(Analog(Bool()))
}
case class C() extends Component{
val AInst=A()
val BInst=B()
AInst.data<>BInst.data
}

I use this way to warp ddr ctrl ip and ddr model by blackbox in simualtion

PasCal++

@volatile-static

  case class A() extends Component {
    val d = Bool.asInOut.setAsAnalog
  }
  case class B() extends Component {
    val d = Bool.asInOut.setAsAnalog
  }
  case class C() extends Component {
    val a = A()
    val b = B()
    a.d := b.d
  }

this code generates the same error, both v1.4.0and v1.7.0

Kellen Wang

@kellenwang1017

how to propagate ClockDomain from toplevel to a submodule when submodule declared a ClockDomain.external("ExtClk")?

Kellen Wang

@kellenwang1017

or is there any other way to propagate ClockDomain from top level to a submodule with using parameters?

Dolu1990

@Dolu1990

@yuqi-ali That is weird, i will try it.
also, can you open a github issue to keep track ?

yuqi

@yuqi-feng

@Dolu1990 SpinalHDL/SpinalHDL#781 this one

Dolu1990

@Dolu1990

Ahhh thanks ^^

Kellen Wang

@kellenwang1017

I just proposed an issue: SpinalHDL/SpinalHDL#783, its about if it is possible to add tracible comments in generated HDL labeling its Scala code line:column, borrowing idea from Chisel.

I'm not sure if such idea is discussed before or not

Please close it if it is duplicate

Kellen Wang

@kellenwang1017

I also wonder when would these two new features mentioned in SpinalHDL/SpinalHDL#575 be available: nameWhenByFile, inlineConditionalExpression

Thanks!!! :)

Kellen Wang

@kellenwang1017

@Dolu1990 SpinalHDL/SpinalHDL#781 this one

Are you a fan of XiangShaoYu?

Dolu1990

@Dolu1990

XiangShaoYu

Don't know about it ^^

So about // @[Foo.scala 111:4]
Basicaly, it can be usefull, but it break down realy fast

as soon things are encapsulated into functions which can be called from multiple place it isn't so usefull

For instance :
myStream.stage()

All the thing created into the stage function will be Stream.scala xxx.y which isn't very usefull, you would need kind of the full stack trace XD

that's way in some ways, SpinalHDL focus more on name propagation

Côme

@come_744:tedomum.net

[m]

Which is a really good thing IMHO

Dolu1990

@Dolu1990

https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Structuring/naming.html?highlight=preserving

Kellen Wang

@kellenwang1017

I have a new idea! SpinalHDL/SpinalHDL#786

Is it possible to use SpinalHDL generate XDC or SDC constraint file along with Verilog?

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