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Dolu1990
@Dolu1990
That one is missing
Adding that single line should fix it
Oleg Stepanov
@reostat
so should I just rewrite AsyncMemoryBusFactory? Or should I try some other bus implementation?
Dolu1990
@Dolu1990
The Apb3SlaveFactory is the most tested one
But you can copy past the AsyncMemoryBusFactory, just add that line, that should be fine then
Oleg Stepanov
@reostat
what would be that line in case of AsyncMemoryBusFactory? super.doNonStopWrite(bus.writeData)?
Dolu1990
@Dolu1990
yes
Oleg Stepanov
@reostat
k, lemme try real quick
well, it compiled!
Oleg Stepanov
@reostat
although your mentioning of this bus being the most untested one definitely does not instill any confidence :)
Apb3 is definitely an overkill in my case. I'm working on Z80-based system
would you like me to create a bug report for this or rather a pull request with the fix?
Dolu1990
@Dolu1990
pull request is perfect ^^
Oleg Stepanov
@reostat
done, PR #258
Oleg Stepanov
@reostat

@Dolu1990 so alright, now I have my ROM and RAM defined as Mem, both neatly wrapped up into adapters to BusSlaveFactory thus being completely bus-agnostic. So far so good, right? However, the size of my RAM is way beyond chip's LUT capacity; and the toolchain understandably does not infer it as SPRAM either. Okay, as per documentation I've used .addStandardMemBlackboxing(blackboxAllWhatsYouCan) and now it generates Ram_1w_1rs. So now what? Documentation stops there :(

I mean, on one hand I have Ram_1w_1rs in generated Verilog, on the other hand I have my SB_SPRAM256KA black box in Scala. How do I bridge the gap? I have the following ideas but all of them seem wrong to me:

  1. Write bridging code in Verilog - err, but that wouldn't be the SpinalHDL way, would it?
  2. Write custom memBlackBoxer (perhaps inheriting from PhaseMemBlackBoxingDefault) - but that looks like a lot of work for this seemingly simple task
  3. Don't use Mem at all; instead, attach SB_SPRAM256KA directly to BusSlaveFactory - yet it seems to be not generic and what was the intent for Ram_1w_1rs then, right?
Michael Meier
@distributed

I have set up a number of simulations for a component of mine and I have trouble interpreting the results I am getting.

Inside the component, I have this assertion:

assert(!recordWriteLock, "push first fire while holding record write lock", FAILURE)

When I run it, i might get this: (i seem to depend on random signals, so assertions fail randomly as well)

[info] [Progress] Verilator compilation done in 2386.726 ms
[info] [Progress] Start RecordFifo basic simulation with seed -7657521877275568118, wave in /home/joe/FPGA/prj/hdl/cisc/./simWorkspace/RecordFifo/basic.vcd
[info] [Done] Simulation done in 26.360 ms
[info] [Progress] Start RecordFifo oneoverflow simulation with seed -7497477908939138281, wave in /home/joe/FPGA/prj/hdl/cisc/./simWorkspace/RecordFifo/oneoverflow.vcd
[info] FAILURE push first fire while holding record write lock
[info] - /home/joe/FPGA/prj/hdl/cisc/tmp/job_1/RecordFifo.v:87: Verilog $finish
[info] FAILURE push first fire while holding record write lock
[info] - /home/joe/FPGA/prj/hdl/cisc/tmp/job_1/RecordFifo.v:87: Verilog $finish
[info] - /home/joe/FPGA/prj/hdl/cisc/tmp/job_1/RecordFifo.v:87: Second verilog $finish, exiting
[success] Total time: 9 s, completed Jan 16, 2020, 10:26:36 AM

I have set up 4 different simulations, however here I am only seeing two of them mentioned, basic.vcd and oneoverflow.vcd.

  • Can I assume that the failure happened in trace oneoverflow.vcd, because it's the last one printed before the error?
  • Because it's a FAILURE, simulation stops right when the assertion fails. Time is not printed. How would I spot the failed assertion when it's just an ERROR?
  • Why is the overall process (last line) successful even if the simulation failed?
jijingg
@jijingg
image.png
hi @Dolu1990 , How to set the default value of port to Xstate instead of random value when simulation starts
jijingg
@jijingg
Normally, as long as it is not assigned, all input and registers are ‘x ’ state
Dolu1990
@Dolu1990
@reostat SB_SPRAM256KA Can't be mapped to Ram_1w_1rs but could be to Ram_1rw (not sure about the name)
Personnaly, for SoC using Ice40 which need that infer SB_SPRAM256KA , i implemented a specific ram peripheral which explicitly use it
Trying to infer things is realy a paine
Writing a custom memBlackBoxer would be the cleaner way
@distributed Hmm i should test Verilog assertion when using SpinalSim
Honnestly, i never realy tried them together

Why is the overall process (last line) successful even if the simulation failed?

That's something i would have to figure out, how to catch assert failure from the verilator, and bring them back to SpinalSim

@jijingg In SpinalSim ?
jijingg
@jijingg
yes spinal Sim
Dolu1990
@Dolu1990
can't do
The simulation backend is verilator
jijingg
@jijingg
or can there have method automatic initial all inputs ports to zero, not init manually one by one
Dolu1990
@Dolu1990
Currently, has to be done manualy
or using "reflection" like things
myBundle.flatten.foreach( ...)
jijingg
@jijingg
OK got,thanks
Michael Meier
@distributed
@Dolu1990 Would you like me to open an issue for this on Github, to keep track of it?
Dolu1990
@Dolu1990
@distributed Yes, thanks :)
Michael Meier
@distributed
Will do! :)
Michael Meier
@distributed

I would like to build a bus slave, APB for now, that maps read or writes to certain addresses to Mem reads/writes. The memory will be shared with other logic, so there needs to arbitration. As far as I can see the BusSlaveFactory does not offer a precooked way of doing this. Note that I do not want to expose a whole memory with readSyncMemWordAligned and friends. The memory should have one read and one write port in order to infer the right kind of RAM in FPGA.

I have the following idea to achieve this, illustrated with how I would implement the write path: Subclass Apb3SlaveFactory and add new methods to describe the accesses. There should be a writeRAMMappedRegs() that has a nonStopWrite(writeStream.payload) to the Stream that goes into the memory. The writeStream.valid is set with onWritePrimitive. Also, the method will call writeHalt when !writeStream. That way the bus write will be delayed until the data made its way into the RAM.

The read path would be similar, except that it has to generate one read request and readHalt until readDataStream.fire.

Is this a feasible way? Is there something simliar that I overlooked?

Oleg Stepanov
@reostat
@Dolu1990 so what's the point of having those default black boxes to Ram_xxx if there's not much you can do about it beside implementing your own blackBoxer or custom BusSlaveFactory attachment? I mean, give me a hint for a generic implementation and I'll be happy to provide a PR for it.
And why do you think SB_SPRAM256KA can't be mapped to Ram_1w_1rs?
Winston Lowe
@wel97459
Is there a way to dynamically add and remove io in a Bundle? I'm making a seven-segment driver but I want it to be able to scale from one segment to X number of segments.
Oleg Stepanov
@reostat
@wel97459 I think you just pass the number of segments you want to drive as a parameter and then define your io parameterized. Something like this:
class SegmentDriver(segmentsNum: Int) extends Component {
  val io = new Bundle {
    val segments = out Vec(Bits(7 bits), segmentsNum)
    // ... other io
  }
  // logic
}
Winston Lowe
@wel97459
oh that make senes
bellaz89
@bellaz89
Hi @Dolu1990 ,
bellaz89
@bellaz89
Am I wrong or the development of the floating support in spinalhdl is a bit stale? Just asking to know if the development of it is happening somewhere else than lib.experimental.math
Dolu1990
@Dolu1990
@bellaz89 that's right
I think to make it moving forward, somebody which has a practical usage of it would have to mature it
Winston Lowe
@wel97459
@Dolu1990 I used the SlowArea class and noticed that components under it, do not use it as the clock source but instead use the clock source driving the SlowArea. val areaDiv10 = new SlowArea(10){ val someClasscomponent = new Classcomponent() } is that as instead?
Winston Lowe
@wel97459
hmm, never mind. it must be something I did I'm looking into it more.