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    Dolu1990
    @Dolu1990
    ok ^^
    A.M.
    @allexoll
    again, i’m happy to do it, some doc is better than none,
    Dolu1990
    @Dolu1990
    sure :)
    And in the hardware documentation it could also point to the software driver
    A.M.
    @allexoll
    yep
    it can be either in the scala file, or in the RTD, or both, whichever you think makes the most sense going forward
    Dolu1990
    @Dolu1990
    RTD <3 => has the doc
    scala => has a link to the RTD
    A.M.
    @allexoll
    👍🏼
    infphyny
    @infphyny

    @Dolu1990 , unfortunately, the vexriscv.demo.GenCustomInterrupt don't compile with VexRiscv dev and SpinalHDL dev on my computer. But Murax demo for example compile fine.

    [info] Running (fork) vexriscv.demo.GenCustomInterrupt 
    [info] [Runtime] SpinalHDL v1.4.4    git head : 48334022505d98fe4f044477c4b0f77d64cece02
    [info] [Runtime] JVM max memory : 14292,0MiB
    [info] [Runtime] Current date : 2021.06.14 10:17:41
    [info] [Progress] at 0,000 : Elaborate components
    [info] ERROR !
    [info] A null pointer access has been detected in the JVM.
    [info] This could happen when in your SpinalHDL description, you access an signal which is only defined further.
    [info] For instance :
    [info]   val result = Bool
    [info]   result := a ^ b  //a and b can't be accessed there because they are only defined one line below (Software rule of execution order)
    [info]   val a,b = Bool
    [info]           
    [error] Exception in thread "main" java.lang.NullPointerException
    [error]     at vexriscv.plugin.CsrPlugin.r(CsrPlugin.scala:514)
    [error]     at vexriscv.plugin.UserInterruptPlugin.setup(CsrPlugin.scala:1318)
    [error]     at vexriscv.plugin.UserInterruptPlugin.setup(CsrPlugin.scala:1310)
    [error]     at vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
    [error]     at vexriscv.Pipeline$$anonfun$build$2.apply(Pipeline.scala:47)
    [error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
    [error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
    [error]     at vexriscv.Pipeline$class.build(Pipeline.scala:47)
    [error]     at vexriscv.VexRiscv.build(VexRiscv.scala:122)
    [error]     at vexriscv.Pipeline$$anonfun$1.apply$mcV$sp(Pipeline.scala:161)
    [error]     at spinal.core.Component$$anonfun$prePop$1.apply(Component.scala:143)
    [error]     at spinal.core.Component$$anonfun$prePop$1.apply(Component.scala:141)
    [error]     at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
    [error]     at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
    [error]     at spinal.core.Component.prePop(Component.scala:141)
    [error]     at spinal.core.Component.postInitCallback(Component.scala:151)
    [error]     at vexriscv.demo.GenCustomInterrupt$.cpu(GenCustomInterrupt.scala:11)
    [error]     at vexriscv.demo.GenCustomInterrupt$$anonfun$1.apply(GenCustomInterrupt.scala:71)
    [error]     at vexriscv.demo.GenCustomInterrupt$$anonfun$1.apply(GenCustomInterrupt.scala:71)
    [error]     at spinal.core.internals.PhaseCreateComponent$$anonfun$impl$2.apply$mcV$sp(Phase.scala:2227)
    [error]     at spinal.core.internals.PhaseCreateComponent$$anonfun$impl$2.apply(Phase.scala:2222)
    [error]     at spinal.core.internals.PhaseCreateComponent$$anonfun$impl$2.apply(Phase.scala:2222)
    [error]     at spinal.core.fiber.Engine$$anonfun$create$1.apply$mcV$sp(AsyncCtrl.scala:144)
    [error]     at spinal.core.fiber.AsyncThread$$anonfun$1.apply$mcV$sp(AsyncThread.scala:58)
    [error]     at spinal.core.fiber.EngineContext$$anonfun$newJvmThread$1.apply$mcV$sp(AsyncCtrl.scala:39)
    [error]     at spinal.sim.JvmThread.run(SimManager.scala:51)
    [error] Nonzero exit code returned from runner: 1
    [error] (Compile / run) Nonzero exit code returned from runner: 1
    [error] Total time: 106 s, completed 2021-06-14 10:17:42

    With VexRiscv dev and SpinalHDL master , I got Missing required plugin: idsl-plugin. I will try to modify the build.sbt script to see if I am able to compile with Riscv dev and
    HDL master

    A.M.
    @allexoll
    in either saxonSoc or VexRiscv there’s an example in the build.sbt on how to do that so it doesn’t rely on the released spinalHDL, but on the local one
    A.M.
    @allexoll
    i had that issue at some point, if you modify the build.sbt to rely on the local plugins it should work
    Jordi
    @JordiVM
    Writetransaction_before_BVALID.png
    I am observing a weird behavior on AXI arbiter. There is a Write access before prior B response from the same master and slave, picture above.
    Prior accesses B valid is asserted before the next ARW transaction, but not on the last one.
    Jordi
    @JordiVM
    Is that expected behavior?
    typingArtist
    @typingArtist
    Perhaps I’m missing the point, but isn’t it the other way round, that the next ARW transaction happens before the last B valid is indicated? Then it is completely valid AXI behavior, as the master is allowed to issue the next access while the previous write access hasn’t been completed yet. If the slave doesn’t like that, it shouldn’t raise READY on arw before completing the previous access, and if the master doesn’t like that, it should simply wait for VALID on b before issuing the next transaction on arw.
    Jordi
    @JordiVM
    This behavior appears in arbiter. The slave does stall the transaction until B valid is raised.
    Dolu1990
    @Dolu1990
    b transactions aren't realy used by VexRiscv, unless you have SMP
    so right, that b valis may be just from one of the previous transactions
    A.M.
    @allexoll
    i’ve done the PR for some documentation for the PLIC mapper, but shouldn’t the PLIC be in the VexRiscv repo, and not in Spinal?
    Dolu1990
    @Dolu1990
    Plic is a RISC-V thing, not a VexRiscv thing
    so, has to be in SpinalHDl
    A.M.
    @allexoll
    ah ok that’s how you split it
    fair enough
    Dolu1990
    @Dolu1990
    thanks for the PR ^^
    A.M.
    @allexoll
    np
    Jordi
    @JordiVM
    I am interested in PLIC implementation, i tried to configure it and was not able to do so. Thanks for documenting the module @allexoll
    Jordi
    @JordiVM
    So i got another picture from the Arbiter side and the Slave (hbc_mem). I get one read access from master ID 8, then before that one is forwarded to the Slave, another WRITE access from master ID 0, and arbiter drives ARW as READ access (ID 8) and W channel is also driven. There is no match between ARW and W accesses as i would expect from AXI4.
    AXIaccessARW_W.png
    Jordi
    @JordiVM
    Should the slave stall Wchannel until ARWWRITE is high?
    Jordi
    @JordiVM
    I was expecting the Arbiter to drive ARW with write together with W channel access
    typingArtist
    @typingArtist
    AXI4 Read/Write is non-standard, but it’s based on AXI4. AXI4 makes it very clear that write data on the W channel can be indicated by the master before the write address channel AW indicates the respective write location. See A3.3 of the AXI4 specification, e.g. from here: http://www.gstitt.ece.ufl.edu/courses/fall15/eel4720_5721/labs/refs/AXI4_specification.pdf
    The specification also mentiones that, since the W channel can precede the AW channel but doesn’t carry routing information, i.e., the address, the interconnect might need to delay the W channel until it knows the address from the AW channel.
    The Write transaction dependencies in Figure A3–6 get into more detail:
    • […]the slave can wait for AWVALID or WVALID, or both before asserting AWREADY
    • […]the slave can wait for AWVALID or WVALID, or both, before asserting WREADY
    So the slave is allowed to synchronize AW and W on the bus, and it doesn’t need to perform the alignment internally but can flow-control towards the bus master.
    Jordi
    @JordiVM
    Okay, so the "master" (arbiter) can but does not have to align them, then the Slave will have "handle" the case of receiving the WVALID before AWVALID (for example stalling)
    @typingArtist got it thanks :D
    I think synchronizing AW and W on slave fixed the issue
    angeeelcm
    @angeeelcm
    Does anyone know how to use Physical Memory Protection (RISCV) with Murax?
    A.M.
    @allexoll
    regarding the DDR, i managed to get it workign thanks to your example, but i’m wondering if i can use it as i intended. my idea was to build a hex ROM bootloader in the onchipSram, and then build my app in the ddr and branch to 0x80000000 after scan. Does monitor halt reset completely reset the CPU, or does it just branch back to mtInitvec? because if it resets to the bootloader, the scanning will erease the just-loaded app
    A.M.
    @allexoll
    a dma with circularMode + memorytoMemory should be able to do the first polling DMA example right?
    mine is stuck on while(dma_busy())
    Dolu1990
    @Dolu1990
    i guess so yes
    A.M.
    @allexoll
    the interconnect seems correct too:
      interconnect.addConnection(dma.write, fabric.dBusCoherent.bmb)
      interconnect.addConnection(dma.read,     fabric.iBus.bmb)
    Dolu1990
    @Dolu1990
    on what soc are you using it ?
    A.M.
    @allexoll
    saxon but with some modifications
    removed the VGA + audio out channels, added a new one:
     val dma = new DmaSgGenerator(0x80000){
        val m2m = new Area {
          val channel = createChannel()
          channel.memoryToMemory load true
          channel.fixedBurst(64)
          channel.withCircularMode()
          channel.withScatterGatter()
          channel.fifoMapping load Some(0, 256)
          channel.connectInterrupt(plic, 12)
        }
      }
    Dolu1990
    @Dolu1990
    i guess would need to have a wave
    Dolu1990
    @Dolu1990
    VexRiscv / Linux / Doom / OpenTTD
    https://www.youtube.com/watch?v=K5Vv32O9g7Q
    typingArtist
    @typingArtist

    https://www.youtube.com/watch?v=K5Vv32O9g7Q

    <3 <3 <3 ^^
    Not the fastest, but most of that must be blamed on the USB full speed disk memory

    Dolu1990
    @Dolu1990
    Right
    So, when i boot the system using a network file system hosted on my PC, things are ~ 1 time faster ~
    hdparam -t /dev/sda give me about 1.05 MB/s