SpinalHDL/VexRiscv

Dolu1990

@Dolu1990

Hmm i would say, you can take inspiration of UsbOhciGenerator for the DMA stuff

val dma = Handle(slave(Bmb(xxxx)))

interconnect.addMaster(
accessRequirements = BmbParameter(yyyy),
bus = dma
)

gainbrain

@gainbrain

Success! I have the BMB signals on the top module now. Simulation up next. Thank you!

Dolu1990

@Dolu1990

Cool ^^

Tim 'mithro' Ansell

@mithro

https://opensource.googleblog.com/2022/08/GlobalFoundries-joins-Googles-open-source-silicon-initiative.html

Dolu1990

@Dolu1990

Hooooo

That's a big one ^^

Nice :D

Zhou Haoyu

@WHZhou

Hi :), I try to run the LitexGen in the NaxRiscv , and I get this error. Can you help me with it?

Exception in thread "main" java.lang.Exception: Can't find the service naxriscv.fetch.FetchCachePlugin
    at naxriscv.utilities.Framework.getService(Framework.scala:106)
    at naxriscv.utilities.Plugin$class.getService(Framework.scala:66)
    at naxriscv.fetch.FetchAxi4.getService(FetchAxi4.scala:9)
    at naxriscv.fetch.FetchAxi4$$anonfun$1$$anon$1.<init>(FetchAxi4.scala:12)

Dolu1990

@Dolu1990

@WHZhou Hi

Dolu1990

@Dolu1990

I just updated the litex / pythondata-naxriscv

I'm not sure why that issue poped up, what command line did you used to generate the soc ?

Also, be aware, i'm currently in the process of getting debian running

it is nearly functional

but there is a few bugs making things crash

cpu bugs

hopefully it will be soon all fixed XD

Here is for instance how i generate a soc for a board :
python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv --with-video-framebuffer --with-spi-sdcard --with-ethernet --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true' --with-jtag-instruction --build --load

64 bits version

with RVC and FPU

sonycmanvr

@sonycman:matrix.org

[m]

How to generate the NaxRiscV bare core, with all AXI buses?
There is no demo configs just like Vex has...

Zhou Haoyu

@WHZhou

I used the IntelliJ Idea 2021 to generate the soc. I simply pressed the 'run LitexGen' button XD.

Dolu1990

@Dolu1990

@WHZhou how old is you litex version ?

@sonycman:matrix.org So, curently, there is https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/Gen.scala#L34 which is a function which return a list of properly configured plugins which will create a functional NaxRiscv

Then, so far, the AXI bridges are implemented for the peripherals

This message was deleted

And for the memory

via a few plugins

for instance https://github.com/SpinalHDL/NaxRiscv/blob/main/src/main/scala/naxriscv/lsu/DataCacheAxi4.scala

sonycmanvr

@sonycman:matrix.org

[m]

@Dolu1990: thank you!

Zhou Haoyu

@WHZhou

@Dolu1990 the latest version from https://github.com/SpinalHDL/NaxRiscv.git.

And the spinalVersion in 'build.sbt' is '1.7.2'

Zhou Haoyu

@WHZhou

By the way, I modified the 'build.sbt' , otherwise I would get errors while building in IDEA.

val spinalVersion = "1.7.2"

lazy val root = (project in file(".")).
  settings(
    inThisBuild(List(
      organization := "com.github.spinalhdl",
      scalaVersion := "2.11.12",
      version      := "2.0.0"
    )),
    //    scalacOptions +=  s"-Xplugin:${new File(baseDirectory.value + s"/../SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}",
    scalacOptions += s"-Xplugin-require:idsl-plugin",
    libraryDependencies ++= Seq(
      "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion,
      "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion,
      compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion),
      "org.scalatest" %% "scalatest" % "3.2.5",
      "org.yaml" % "snakeyaml" % "1.8"
    ),
    name := "NaxRiscv"
  )
//  ).dependsOn(spinalHdlIdslPlugin, spinalHdlSim,spinalHdlCore,spinalHdlLib)
//lazy val spinalHdlIdslPlugin = ProjectRef(file("../SpinalHDL"), "idslplugin")
//lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim")
//lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core")
//lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib")


fork := true

Dolu1990

@Dolu1990

Ahhh i think "And the spinalVersion in 'build.sbt' is '1.7.2'" is wrong

should be dev :
https://github.com/SpinalHDL/NaxRiscv/blob/main/build.sbt#L1

maybe, can you delete the pythondata_cpu_naxriscv/verilog/ext folder ?

basicaly, the two repo in it are cloned when running the generation

and delete the naxriscv_xxxxx.v

and then send me the litex logs when you run the generation

Zhou Haoyu

@WHZhou

I discarded my changes in 'build.sbt', and manually cloned the https://github.com/SpinalHDL/SpinalHDL.git to the same directory of NaxRiscv. And I get these error logs when I run the generation.

F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\Bits.scala
F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\SInt.scala
F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\Spinal.scala
Error:(364, 51) object Info is not a member of package spinal.core
  val version = (if(Character.isDigit(spinal.core.Info.version(0))) "v" else "") + spinal.core.Info.version
Error:(364, 96) object Info is not a member of package spinal.core
  val version = (if(Character.isDigit(spinal.core.Info.version(0))) "v" else "") + spinal.core.Info.version
Error:(374, 59) object Info is not a member of package spinal.core
    } + s" SpinalHDL $version    git head : ${spinal.core.Info.gitHash}")
F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\Trait.scala
F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\UInt.scala
F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\internals\BackendUtils.scala
Error:(42, 101) object Info is not a member of package spinal.core
    buffer ++= s"$commentSymbol Generator : SpinalHDL ${Spinal.version}    git head : ${spinal.core.Info.gitHash}\n"
F:\Projects\SpinalHDL\core\src\main\scala\spinal\core\internals\Phase.scala

Dolu1990

@Dolu1990

can you show me the Version.scala content ? in spinalhdl/project ?

there is probably something weird somewere in the setup, because NaxRiscv did pass the github actions of the litex repo

Zhou Haoyu

@WHZhou

ok, the Version.scala:

object SpinalVersion {
  val compilers = List("2.11.12", "2.12.13", "2.13.6")
  val compilerIsRC = false

  val isDev = true
  val isSnapshot = false
  private def snapshot = if (isSnapshot) "-SNAPSHOT" else ""
  private val major = "1.7.2"
  val all         = if(isDev) "dev" else s"$major$snapshot"
  val sim         = all
  val core        = all
  val lib         = all
  val ip          = all
  val debugger    = all
  val demo        = all
  val tester      = all
}

Dolu1990

@Dolu1990

that seems good

hmmm

maybe do a sbt clean compile in the SpinalHDL repo, and then in the NaxRiscv repo ?

that's realy weird

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