OpenROAD/community

Guy-Armand Kamendje

@gkamendje_gitlab

On my side double clicking on the images pops up a bigger size image. Please let me know if that works for you too.

Austin Rovinski

@rovinski

@gkamendje_gitlab seems like RePlAce is diverging. I assumed you checked through your log files for warnings and errors? Try playing around with different core utilization values and placement density values (make sure placement density is always greater than core utilization).

Charu

@charumaurya

The commands in OpenSTA.doc like <all_clocks> , <all_registers> return the clocks and registers defirned in .lib file of our design?

Rajarshi Roy

@rjrshr_twitter

@charumaurya <all_clocks> will return the references to the clocks created by the <create_clock> commands. <all_registers> will return references to the flops in the design (.v file) that are driven by the clocks created with the <create_clock> commands

@gkamendje_gitlab what tool do you use to view the design at the various stages of the flow like above? If it is within the OpenROAD flow, what command is it? I am guessing the input are .def files.

Guy-Armand Kamendje

@gkamendje_gitlab

@rjrshr_twitter hello I am using klayout to view the design. I have added the following make targets that allow me view the output of the flow at various stages.

klayout_cts: $(RESULTS_DIR)/4_cts.def $(OBJECTS_DIR)/klayout.lyt
klayout -rd in_def="$<" \
-rd tech_file=$(OBJECTS_DIR)/klayout.lyt \
-rm $(UTILS_DIR)/viewCts.py &

Guy-Armand Kamendje

@gkamendje_gitlab

The inputs are the .def, the tech file and the klayout init file as well the file viewCts.py which is a stripped down version of the file util/viewDrc.py (I just remove the DRC check section of the python script). Alternatively you could use https://edaviewer.com/ (which you can also run locally using docker)

Charu

@charumaurya

@rjrshr_twitter but I am not getting the clock name in the output as defined in my .v

Guy-Armand Kamendje

@gkamendje_gitlab

@charumaurya I guess what you are trying to do is this.
create_clock -name clk1 -period 10 clk1
create_clock -name clk2 -period 10 clk2
create_clock -name clk3 -period 10 clk3
set_input_delay -clock clk1 0 in1
set_input_delay -clock clk2 0 in2

Guy-Armand Kamendje

@gkamendje_gitlab

@rovinski
Hi have the following values
export CORE_UTILIZATION = 25
export CORE_ASPECT_RATIO = 1.0
export PLACE_DENSITY ?= 0.35
However, I do get a negative Filler area error from RePlace (see below). Not sure what is going on here. There should be plenty of space.
[INFO] DBU = 1000
[INFO] SiteSize = (560, 4480)
[INFO] CoreAreaLxLy = (560, 0)
[INFO] CoreAreaUxUy = (146720, 143360)
[INFO] NumInstances = 321
[INFO] NumPlaceInstances = 240
[INFO] NumFixedInstances = 81
[INFO] NumDummyInstances = 0
[INFO] NumNets = 276
[INFO] NumPins = 944
[INFO] DieAreaLxLy = (0, 0)
[INFO] DieAreaUxUy = (148099, 148099)
[INFO] CoreAreaLxLy = (560, 0)
[INFO] CoreAreaUxUy = (146720, 143360)
[INFO] CoreArea = 20953497600
[INFO] NonPlaceInstsArea = 609638400
[INFO] PlaceInstsArea = 7744665600
[INFO] Util(%) = 38.068813
[INFO] StdInstsArea = 7744665600
[INFO] MacroInstsArea = 0
[InitialPlace] Iter: 1 CG Error: 1.12647e-07 HPWL: 10770166
[InitialPlace] Iter: 2 CG Error: 9.66875e-08 HPWL: 9097165
[InitialPlace] Iter: 3 CG Error: 9.76417e-08 HPWL: 9097767
[InitialPlace] Iter: 4 CG Error: 1.1091e-07 HPWL: 9104395
[InitialPlace] Iter: 5 CG Error: 8.13137e-08 HPWL: 9115166
[ERROR] Filler area is negative!!
Please put higher target density or
Re-floorplan to have enough coreArea
(REPL-1)
[INFO] FillerInit: NumGCells = 240
[INFO] FillerInit: NumGNets = 276

Charu

@charumaurya

@gkamendje_gitlab my motive is to generate timings paths in a given design, and since the documentation has a built-in command <find_timing_paths> with arguments like -from [pin|port|net] and -to, while giving this <find_timings_path -from clk1 -to in2> command,

I get same error, that clk1, in2 not defined

@gkamendje_gitlab so I thought of testing these simple commands like <get_clocks> to see what the tool returns. But i guess, I'm missing something

Austin Rovinski

@rovinski

@gkamendje_gitlab @rjrshr_twitter There already exist targets to open a viewer for any DEF or GDS in the results folder. Use make klayout_% where % is the name of the def, e.g. make klayout_2_floorplan.def or make klayout_6_final.gds

@gkamendje_gitlab Your utilization is too high. Replace is reporting it as [INFO] Util(%) = 38.068813, which is greater than your PLACE_DENSITY of 0.35. You need to make sure the area / utilization is getting set correctly and not overridden somewhere.

Austin Rovinski

@rovinski

@charumaurya all_clocks returns a list of database clock objects. If you want the names, you would need puts '[get_name [all_clocks]]'

More specifically if there is more than one clock, foreach clk [all_clocks] {puts [get_name $clk]}

Guy-Armand Kamendje

@gkamendje_gitlab

@rovinski Thanks for the hint I was not aware of the make klayout_% target. This is really cool.

Rajarshi Roy

@rjrshr_twitter

@gkamendje_gitlab @rovinski Thanks for the klayout hint! EDAviewer looks cool too!

Guy-Armand Kamendje

@gkamendje_gitlab

@rovinski I was wondering if there is a way to visualize the inserted clock tree. Any thought on ClipGraphExtract?

@rjrshr_twitter I would strongly recommend that you use the approach suggested by @rovinski . Mine was just a quick hack.

Austin Rovinski

@rovinski

@gkamendje_gitlab it's not the cleanest way but there is a script deleteNonClkNets.tcl which produces a DEF that only has clock nets in it. You can run the script with make $(RESULTS_DIR)/6_final_only_clk.def
It was made as part of a utility target make gallery which creates several layout screenshots representing different design steps.

Guy-Armand Kamendje

@gkamendje_gitlab

@rovinski thanks for the hint. I will have a look at it.

ChibiMarukoZ

@ChibiMarukoZ

@rovinski hello, I have used ICeWall recently, but the net to the I/O cell pin still fails be connected. The main manifestation is that there is no relevant net information in "route.guide". The I/O cell we use has its own PAD, and there is no need to add an additional PAD. Is this the main reason for the failure to connect?
The current situation is as shown in the figure below. In "reality", the green line means that it is connected, and the red line is expected to be connected but not connected (the corresponding NET in def has no ROUTE description).Buffer is added at "Resizing & Buffering".
issue.png

Jonathan Tremesaygues

@killruana

has the flow repo been deleted? https://github.com/The-OpenROAD-Project/OpenROAD-flow

answer found
The-OpenROAD-Project/OpenROAD#408

Painting

@redpanda3

...

ChibiMarukoZ

@ChibiMarukoZ

...

tnt

@tnt_twitter

Is there an explanation of the OpenDB object model / Python API somewhere ? I'm trying to see how I can route things in a DEF.

Austin Rovinski

@rovinski

@tnt_twitter nope, not really. The only tool that really uses the wire API is pdngen. The API for TCL and Python is the same, it is generated from Swig. Although tcl has wrapper procs to do error checking so not exactly the same.

I think we're aiming to start concerted documentation efforts within a few months but I'm not sure. Your best bet until then is looking through header files.

clarkchen900

@clarkchen900

Hi, all. OpenROAD is a very cool tool set! Appreciate all the hardwork behind it.

However I got compilation error on Mac OS X 10.15, like this:

make[2]: Entering directory '/home/OpenROAD/build'
[ 26%] Swig compile /home/OpenROAD/src/OpenDB/src/swig/tcl/opendbtcl.i for tcl
cd /home/OpenROAD/build/src && /usr/local/bin/cmake -E make_directory /home/OpenROAD/build/src /home/OpenROAD/build/src/CMakeFiles/opendb_swig.dir
cd /home/OpenROAD/build/src && /usr/local/bin/cmake -E touch /home/OpenROAD/build/src/CMakeFiles/opendb_swig.dir/opendbtclTCL.stamp
cd /home/OpenROAD/build/src && /usr/local/bin/cmake -E env SWIG_LIB=/usr/share/swig/2.0.10 /usr/bin/swig -tcl -module opendbtcl -namespace -prefix odb -w509,503,501,472,467,402,401,317,325,378,383,389,365,362,314,258,240,203,201 -I/home/OpenROAD/src/OpenDB/include/opendb -I/home/OpenROAD/src/OpenDB/src/swig/tcl -outdir /home/OpenROAD/build/src -c++ -o /home/OpenROAD/build/src/CMakeFiles/opendb_swig.dir/opendbtclTCL_wrap.cxx /home/OpenROAD/src/OpenDB/src/swig/tcl/opendbtcl.i
/home/OpenROAD/src/OpenDB/include/opendb/db.h:5871: Error: Syntax error in input(3).
make[2]: [src/CMakeFiles/opendb_swig_swig_compilation.dir/build.make:68: src/CMakeFiles/opendb_swig.dir/opendbtclTCL.stamp] Error 1
make[2]: Deleting file 'src/CMakeFiles/opendb_swig.dir/opendbtclTCL.stamp'
make[2]: Leaving directory '/home/OpenROAD/build'
make[1]: [CMakeFiles/Makefile2:341: src/CMakeFiles/opendb_swig_swig_compilation.dir/all] Error 2
make[1]: Leaving directory '/home/OpenROAD/build'
make: [Makefile:133: all] Error 2

in Docker openroad/openroad:base

Austin Rovinski

@rovinski

@clarkchen900 your swig version is too old. Try using swig 4.0 or newer

clarkchen900

@clarkchen900

@rovinski Thanks! yeah it is the problem. I was compiling in the openraod/openroad:base Docker, somehow the swig come with it is version 2.0.10, very old. I thought the Docker had come with the right dependent software...

Austin Rovinski

@rovinski

@clarkchen900 It does: https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/Dockerfile#L34-L42

Akshaygireesh

@Akshaygireesh

can anyone help me out with installation of openROAD in ubuntu 18.04

@promach how did you install it via archlinux git

Jiuyang Liu

@sequencer

OpenROAD didn’t bump swig to 4

Which caused archlinux building failed.

Akshaygireesh

@Akshaygireesh

@sequencer could you please help me with installation in ubuntu

Jiuyang Liu

@sequencer

Sorry I have no knowledge to Ubuntu...

I suggest you use docker instead.

promach

@promach

@Akshaygireesh arch linux != ubuntu

clarkchen900

@clarkchen900

@rovinski Thanks - it worked! Will try more on the openroad toolset. Cheers,

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