For instance see pitch information for Nangate45 here: https://github.com/The-OpenROAD-Project/alpha-release/blob/master/flow/platforms/nangate45/NangateOpenCellLibrary.mod.lef#L20
I was thinking since I'm going through the process of setting up a technology it might be worth me documenting it in a step by step guide which others could use in the future. Is this something you'd welcome and if so where would be the best place to put the info? A README in alpha-release/flow/platforms?
@yrrapt Yes please! Any contributions and documentation (or fixes to existing documentation) is welcome. Depending on how long it is we can add it to this page (https://github.com/The-OpenROAD-Project/alpha-release/blob/master/flow/README.md) or create a new page (as you've suggested) and link from there. Thanks
Hi, all. OpenROAD looks like a very exciting WIP. Step 2 of https://github.com/The-OpenROAD-Project/alpha-release/tree/develop/flow "Running the Flow" is "An OpenROAD release must be setup to run the tests. More info in the build README". "README" is a broken link. So, 1) where is this supposed to point, and 2) is this flow ready to try?
Hi @stevehoover
Please, refer to the
The
Please, refer to the
master branch at https://github.com/The-OpenROAD-Project/alpha-release/tree/master/flowThe
develop branch is .. still being developed :)
Sorry for the late response. Can you start from the home page https://flow.theopenroadproject.org/ to create an account (using the Get Started Button), not the login page directly. I reported the issue with the login page that does not give a proper error message.
In the documentation on the Cloud Flow there is reference to the template repository but I can't access that repository.
The same for the RISCV example.
But this is example is available https://github.com/abdelrahmanhosny/FlowRunnerAESExample
[WARNING] Failed to open file /openroad-sandbox/d8e38a12-3211-4eb8-98cf-80d3e0e9a4c0/flow_output/objects/../../..//openroad-sandbox/d8e38a12-3211-4eb8-98cf-80d3e0e9a4c0/flow_output/tech/merged_padded.lef
Hi @Fatsie_gitlab and @kareefardi
Thanks for your interesting in trying the flow. I added a reply to the issue on GitHub: abdelrahmanhosny/FlowRunnerAESExample#2
Thanks for your interesting in trying the flow. I added a reply to the issue on GitHub: abdelrahmanhosny/FlowRunnerAESExample#2
I have a question regarding tritonCTS. I wanted to know what does the argument
Also In general CTS docs and readme(s) are slightly outdated.
percentile refer to.Also In general CTS docs and readme(s) are slightly outdated.
Hi, everyone. I'm redpanda3. Author of soDLA(https://github.com/soDLA-publishment/soDLA), exploring a new way to develop open-source hardware.
Hi @redpanda3, you are more than welcome to try out OpenROAD. We recommend using the alpha release located here: https://github.com/The-OpenROAD-Project/alpha-release. We are currently working towards a new release of the tools of the tools in January. This release is available here, but is not yet stable: https://github.com/The-OpenROAD-Project/OpenROAD
@dwisehart You can view our supported nodes under the platform section of OpenROAD-flow/flow/README.md. TSMC65lp is a supported node. We can't provide you the config files for TSMC65lp due to NDA reasons, but if you are able to recreate the config files (using Nangate45 as a guide) then it should work.
I'm trying to build openroad on an ubuntu machine using docker following https://github.com/The-OpenROAD-Project/OpenROAD-flow/blob/master/README.md
I get this error after everything else has run successfully https://imgur.com/a/DkCD1HV
@rovinski it seems that you added these lines.
get the same error if i source from other dir
I have a question. I'd like to report my design's area as NAND-gate equivalent, so I need to get the exact area for NAND2 gates the library. Which command in the flow can I use to get that value?
Hi @kammoh,
Thanks, glad the tool is working well for you.
The DB interface is not exactly clean-facing towards the end-user right now. Here is an example script that can get the cell area based on the name:
read_lef platforms/nangate45/lef/NangateOpenCellLibrary.macro.mod.lef
set cell_name NAND2_X1
set lib_name [[ord::get_db] getLibs]
set cell_master [$lib_name findMaster $cell_name]
set height [$cell_master getHeight]
set width [$cell_master getWidth]
set dbu [$lib_name getDbUnitsPerMicron]
set area [expr 1.0 * $height * $width / $dbu / $dbu]
puts "Cell $cell_name area: $area um^2"Alternatively you can just look up the cell in your LEF file and find the SIZE property, e.g.
MACRO NAND2_X1
CLASS CORE ;
ORIGIN 0 0 ;
FOREIGN NAND2_X1 0 0 ;
SIZE 0.57 BY 1.4 ;
Hi everyone !
I gave a try (mainly for curiosity purposes) to OpenROAD and it looks promising !
Did you guys considered adding VHDL support through GHDL (or at least suggest it) since it can be plugged quite nicely into yosys (Check the ghdlsynth-beta yosys module repository) ?
I tried yesterday to read a vhdl design, then output it as synthetized verilog, then load this verilog in OpenROAD, and it seemed to work quite nicely.
I gave a try (mainly for curiosity purposes) to OpenROAD and it looks promising !
Did you guys considered adding VHDL support through GHDL (or at least suggest it) since it can be plugged quite nicely into yosys (Check the ghdlsynth-beta yosys module repository) ?
I tried yesterday to read a vhdl design, then output it as synthetized verilog, then load this verilog in OpenROAD, and it seemed to work quite nicely.
Hi @suzizecat,
For HDL parsing we are focused only on what yosys provides, which is Verilog with some limited support of System Verilog. OpenROAD is a modular tool that uses open-source formats for design exchange (lib, v, LEF, DEF, SDC, SPEF, etc.). If you want to replace a tool with one that offers legal output in those formats, then you are more than welcome to.
For HDL parsing we are focused only on what yosys provides, which is Verilog with some limited support of System Verilog. OpenROAD is a modular tool that uses open-source formats for design exchange (lib, v, LEF, DEF, SDC, SPEF, etc.). If you want to replace a tool with one that offers legal output in those formats, then you are more than welcome to.
Hi @rovinski ,
Thanks for your answer ! Just to be sure that there is no misunderstanding, GHDL is also free and open-source, and provide a yosys module which allows you to read a VHDL file using (from within yosys) :
I don't want to be that guy telling "it's easy, why don't you do it ?", just bringing up the existence of the tool if you didn't knew about it :wink: .
Thanks for your answer ! Just to be sure that there is no misunderstanding, GHDL is also free and open-source, and provide a yosys module which allows you to read a VHDL file using (from within yosys) :
ghdl your_top (By that, I mean that there is not much work to do to add the support). You don't have to replace anything and can (probably) mix vhdl and verilog using this.I don't want to be that guy telling "it's easy, why don't you do it ?", just bringing up the existence of the tool if you didn't knew about it :wink: .
@suzizecat message understood. We are currently focused on stability and correctness of OpenROAD for the next several months, which includes better CI, automating manual steps, and reducing errors and DRVs down to 0 on our benchmark designs. We have a tapeout in an advanced node coming up as part of our funding contract that we are required to meet. Because of this, all of our development resources are focused on these topics.
That being said, I am glad that you are able to get a VHDL flow running with little effort and OpenROAD works for your purposes. Note that we are open to pull requests!
Hi there, I performed a timing check on a dummy design and don't understand a part of the result. In the following (extract from timing report) :
0.03 1.54 v _3113_/Y (AOI21X1)
0.06 1.60 ^ _3171_/Y (OAI21X1)What does mean v and ^ (and is there a documentation where this is described and that I may have missed ?)
@suzizecat
^ and v indicate whether the transition at the pin is a rising edge or a falling edge. I took a quick peek through the OpenSTA documentation and I don't think there is anything specific on the format of the timing reports, but this is fairly standard syntax across different static timing engines.
Hi !
In order to compile TritonRouter, I had to edit the CMakeLists.txt as follow because some files doesn't exists :
set (FLEXROUTE_HEADER
${FLEXROUTE_HOME}/src/drc/frDRC.h
${FLEXROUTE_HOME}/src/FlexRoute.h
# ${FLEXROUTE_HOME}/src/io/frGuidePrep.h
${FLEXROUTE_HOME}/src/io/frAPG.h
${FLEXROUTE_HOME}/src/io/frPinPrep.h
${FLEXROUTE_HOME}/src/io/io.h
${FLEXROUTE_HOME}/src/io/frShapeUtil.h
# ${FLEXROUTE_HOME}/src/io/frUtil.h
...Is there an issue on my end or something's wasn't updated properly to github ?