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    anik_balo
    @anik_balo:matrix.org
    [m]
    anik_balo
    @anik_balo:matrix.org
    [m]
    ufukyill
    @ufukyill
    Where should i post my issue about OpenLane flow? I need link pls.
    1 reply
    ufukyill
    @ufukyill
    image.png
    20 replies
    Im having this error in the "run_placement" phase . run_synthesis and run_floorplan phases was successful. Any idea about what should i do ?
    ufukyill
    @ufukyill
    image.png
    mik1234mc
    @mik1234mc
    image.png
    1 reply
    Hi all, I am compiling OpenROAD and facing the follwoing error. Any idea what is wrong?
    ufukyill
    @ufukyill
    Screenshot from 2022-01-02 16-05-29.png
    1 reply
    While i was running run_routing i faced with this situation. Is there any problem or it is normal?
    1 reply
    Im still waiting
    anik_balo
    @anik_balo:matrix.org
    [m]
    Can I observe timing , power, area report in yosys? any idea?
    1 reply
    Aireen Amir
    @AmirAireen_twitter
    image.png
    4 replies
    sharjeel
    @microSharjeel
    I am encountering following error while placing a Macro in my design
    Traceback (most recent call last):
    File "/openLANE_flow/scripts/manual_macro_place.py", line 119, in <module>
    assert not macros, ("Macros not found:", macros)
    AssertionError: ('Macros not found:', {'ram': ['5590', '168230', 'N']})
    2 replies
    kindly guide me what is the problem
    ufukyill
    @ufukyill
    Can i run through flow each module of my rtl design seperately and assemble it after flow? Is there a way to do that?
    bosje
    @bosje:matrix.org
    [m]
    Hey! I have a design which I synthesized with yosys and the freePDK45 lib, I'd like to get some idea about the timing and critical path of the design, as well as maximum frequency. Can I use openSTA for this? Im having trouble finding some examples to do this
    2 replies
    anik_balo
    @anik_balo:matrix.org
    [m]
    2 replies
    How can I create this kind of gif or visualization in OpenRoad flow? Can anyone guide me?
    anik_balo
    @anik_balo:matrix.org
    [m]
    How to find or by which command we can get the number of cell or instance used in a design in OpenRoad?
    5 replies
    Neil Howard
    @TheNeilHoward_twitter
    I am setting up a new target technology. A test design gets through to detailed routing and then terminates with...
    [[[
    ...
    [INFO DRT-0081] Complete 962 unique inst patterns.
    @@@ dead end inst
    @@@ dead end inst
    [ERROR DRT-0085] Valid access pattern combination not found.
    terminate called after throwing an instance of 'std::runtime_error'
    what(): DRT-0085
    ]]]
    Any clues?
    1 reply
    Tom Spyrou
    @tspyrou
    @TheNeilHoward_twitter are you able to file a github issue with the testcase? I am sure we can help you work through how to specify the rules. If it is a testcase that needs to be closed source or have an NDA then mention email me at tspyrou@precisioninno.com .
    @ufukyill The flow for this is in our plans but has not been developed yet.
    dralabeing
    @dralabeing
    Check out #Openroad based summer internship projects as part of the OSRE initiative in the link below. It's a great way to directly contribute to the OpenROAD project. If you have any other project ideas or need details, email me at dralabeing@openroad.tools.
    Projects: https://github.com/uccross/uccross.github.io/blob/master/projects.md
    Applications: https://cross.ucsc.edu/2022-osre/osre2022apps.html
    Anik Balo
    @anikbalo:matrix.org
    [m]
    There is a "DEFAULT NAMING CONVENTIONS OF INSTANCES" available for genus, innovus. From where we can guess instance naming pattern for most of the stages(like during tech mapping, default name prefix of combinational instance is "g*"). Is there anything like that in OpenROAD, which can tell us what will be the default naming pattern of instances in major steps(like synthesis, placement, routing, add filler)?
    Anik Balo
    @anikbalo:matrix.org
    [m]
    :point_up: Edit: There is a default naming conventions of instances available for genus, innovus. From where we can guess instance naming pattern for most of the stages(like during tech mapping, default name prefix of combinational instance is "g*"). Is there anything like that in OpenROAD, which can tell us what will be the default naming pattern of instances in major steps(like synthesis, placement, routing, add filler)?
    1 reply
    DanielaSanchezL
    @DanielaSanchezL

    Hi,

    could anyone please help me?

    I was generating some reports and saving them into separated files with an old version.
    Using the new OpenROAD Version 2b735353d335c9321f67731e56d2d61b4c8b78d2, the following commands do not work anymore :

    report_power -digits 7 >> power.rpt

    with_output_to_variable r "report_power -digits 7 " puts $r
    (the report command runs successfully, but the file power.rpt is empty and $r prints an empty line)

    Does some know how to save the output to report_* to separated files?
    Thanks and sorry for the dumb question!

    Tom Spyrou
    @tspyrou
    @DanielaSanchezL, The redirect is a feature that we lost when we upgraded to the spdlog logger. We will look at fixing it, but at the moment it is not working.
    1 reply
    jimbo1990
    @jimbo1990
    Openlane is hanging at report_clock_skew never passes anyone heard of this before?
    5 replies
    Anik Balo
    @anikbalo:matrix.org
    [m]
    3 replies
    I was trying to implement a big design in Openroad but failed. Any suggestion or help on that?
    Guytout
    @gkamendje
    is there a tutorial that illustrates how to do floorplaning at the macro level? Right now the power grid strategy is defined in the pdn.cfg file at the platform level. Is there a way to do this at the design/block level without affecting the platform strategy?
    3 replies
    Is there a tutorial that illustrates how to insert Tie cells, Filler cells and Decap cells in the flow? I do see the file platforms/sky130hd/fill.json. How is this file use? How is this file generated?
    Guytout
    @gkamendje
    I am getting the following error:
    [ERROR GRT-0061] Layer NW is less than the min routing layer (METAL1)
    Error: fastroute.tcl, 1 GRT-0061.
    I have a custom platform with the following in the config.mk file
    export MIN_ROUTING_LAYER = 1
    export MAX_ROUTING_LAYER = 5
    and in fastroute.tcl I do have the following line
    set_global_routing_layer_adjustment $::env(MIN_ROUTING_LAYER)-$::env(MAX_ROUTING_LAYER) 0.5
    It looks like layer NW is seen as a routing layer.
    whereas it should be seen as a power layer. In the pdn.cfg I do set a global connection to VDD on all VNW pins
    3 replies
    Grant Brown
    @GrantBrown1994
    Does OpenROAD have a LVS tool built into its flow? What are people using to do LVS for MPW5, previously we used Calibre however we want to do this fully open source.
    1 reply
    im assuming its netgen.
    Muhammed Conger
    @muhammedconger
    Aranızda türk olan veya türkçe bilen var mı?
    stefanottili
    @stefanottili

    M1 MacBook MacOS Monterey 12.3

    build_openroad.sh --local gets very far, but then fails to find the lemon includes.

    I've manually installed lemon-1.3.1 in OPENROAD directory parallel to OpenRoad-flow-scripts.
    Setting LEMOND_DIR to the cmake directory doesn't seem to be sufficient.
    What am I missing ?

    cd OpenROAD-flow-scripts
    export LEMON_DIR=<abs-path>/OpenROAD/lemon-1.3.1/build/cmake
    ./build_openroad.sh --local
    ....
    [ 95%] Built target rmp
    OpenROAD-flow-scripts/tools/OpenROAD/src/dpo/src/detailed_mis.cxx:48:10: fatal error: 'lemon/cost_scaling.h' file not found

    4 replies
    stefanottili
    @stefanottili

    After installing lemon correctly, build_openroad.sh --local did build the openroad and sta executables on a M1, but it got stuck compiling LSOracle.
    Does anybody familiar with how the cxx flags get generated with cmake how to change -march=native to -mcpu=apple-a14 ?

    [INFO FLW-0019] Compiling LSOracle.
    -- Build type is 'RELEASE'
    -- CMAKE_CXX_FLAGS_RELEASE: -O3 -DNDEBUG -O3 -mtune=native -march=native
    [ 50%] Building CXX object lib/kahypar/CMakeFiles/mini_boost.dir/program_options/src/positional_options.cpp.o
    clang: error: the clang compiler does not support '-march=native'

    4 replies
    ABDUR Rahman
    @humptys:matrix.org
    [m]
    hello gys can someone help me with a error im gettign while trying for STA
    1 reply
    YehowshuaMotivo
    @YehowshuaMotivo

    I've been studying the TritonCTS code within OpenRoad and I would like to write my own timing closer passes - that is, being able to decide when to add buffers, and then check if there are no violations.

    I'm wondering if anybody has any pointers...

    YehowshuaMotivo
    @YehowshuaMotivo
    I should mention - I might be able to pay for help to modify TritonCTS in this manner.
    1 reply
    dralabeing
    @dralabeing
    @BetterCoder4 Please reach out via email to Tom Spyrou aspyrou@eng.ucsd.edu OoenROAD project architect with your proposal
    Guytout
    @gkamendje
    Is it possible to manually specify the pins locations instead of having a complete random placement.
    I do see the following directive used in https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/designs/gf12/swerv_wrapper/config.mk
    export PLACE_PINS_ARGS = -exclude left: -exclude right: -exclude top:* -exclude bottom:0-10 -exclude bottom:400-700
    Can I use PLACE_PINS_ARGS to specify the location of the pins? If yes what is the syntax to be used?
    Where can I find the documentation around PLACE_PINS_ARGS?
    4 replies
    Qianpeng Li
    @QianpengLi577
    Hi, anyone could tell me how to add new paltform in OpenRoad-flow-scripts? I have seen the guide in https://openroad.readthedocs.io/en/latest/contrib/PlatformBringUp.html , but I dont know how to get the file under flow/platform/mynewplatform/ .Though I get NCSU-FreePDK-15 design file, these files are different from flow/platform/nangate45/* . Thanks.
    4 replies
    GuzTech
    @GuzTech

    Hello everyone!

    I'm in the process of bringing up a new platform which is going well. I am running into a problem with a local interconnect layer which is specified as a masterslice with LEF58_TYPE = MEOL. OpenDB complains that there is a parse mismatch for this lil layer.
    If I add this lil layer as a routing layer then OpenDB complains that it is not a routing layer. If I don't add lil as a routing layer, then TritonRoute gives an error that it cannot find layer lil for viarule that connects lil to the first metal layer.

    Did anyone else run into a similar problem? If so, how did you solve it?

    3 replies
    Guytout
    @gkamendje

    I have installed the yosys-uhdm plugin so that I could read SystemVerilog source files directly during synthesis.
    I am using the ORFS.
    I use -m systemverilog to load the systemverilog plugin during Yosys startup.

    I have the following lines in my design/config.mk file

    export YOSYS_READ_SV = 1
    export VERILOG_FILES = /full_path_to_rtl/my_defs_pkg.sv \
                           /full_path_to_rtl/module1.sv     \
                           /full_path_to_rtl/module2.sv     \
                           /full_path_to_rtl/top.sv

    I have also modified the file scripts/synth_preamble.tcl to look like this:

    if {[info exist ::env(YOSYS_READ_SV)]} {
    # Read SystemVerilog Files
    
    # ======> Trial 1) This does not work either <========
    #read_systemverilog -defer {*}$vIdirsArgs -DSYNTHESIS -sverilog $::env(VERILOG_FILES) 
    
    
    # ======>Trial 2)  This does not work <================
    #foreach file $::env(VERILOG_FILES) {
    #read_systemverilog -defer -verbose -d 2 {*}$vIdirsArgs -DSYNTHESIS -sv $file
    #    
    #}
    
    
    
    # =====> Trial 3) This works but it is now what I want <========================
    read_systemverilog -DSYNTHESIS -sv {*}$vIdirsArgs \
                /full_path_to_rtl/my_defs_pkg.sv      \
                /full_path_to_rtl/module1.sv          \
                /full_path_to_rtl/module2.sv          \
                /full_path_to_rtl/top.sv                
    
    
    } else {
     #Read verilog files
     foreach file $::env(VERILOG_FILES) {
      read_verilog -defer -sv {*}$vIdirsArgs $file
     }
    
    }

    I don't know if this is an issue with the way the variable $::env(VERILOG_FILES) is passed to read_systemverilog or something else
    but:
    for trial 1) above, the script complains that the file 'all_the_files_names_together_separated_with_a_blank' cannot be found for read
    For trial 2) the lower level modules (module1.sv and module2.sv) are not elaborated/compiled and I also get the message [ERR:EL0528] undefined package "my_desf_pkg".
    Trial 3 works but it is not exactly what I am looking for since I am hard coding the file names in the synthesis script.
    Could someone shed some light on what is going on here?

    2 replies
    Julien FAUCHER
    @suzizecat
    Hi there !
    I found ressources (mainly an article from antmicro) mentionning the possibility to hook up Surelog/UHDM+YOSYS at the input of open lane flow, but either I'm bad at it or whatever, but I never managed to make it work. Did someone managed to input fully fledged SV as input for OpenLane/OpenROAD ?
    5 replies
    Raotanuj
    @Raotanuj
    Hey Everybody
    I have just started using Openlane.
    I m repeatedly incurring PDN pitch error on trying the flow with a Ripple counter RTL Code. The error is like this:
    [ERROR PDN-0085] Pitch 3.6799999999999997 specified for layer met4 is less than 2 x (width + spacing) (width=1.6, spacing=1.84).
    Any help is appreciated.
    1 reply