OpenROAD/community

441357546

@441357546

@quentinw91 Appreciate for your help,i will try it later.Thanks ！！ i will tell u if i get advance.

Austin Rovinski

@rovinski

Manual CTS characterization is supposed to eventually go away in favor of automatic characterization... but I still don't know when that's supposed to happen. I was hoping it was going to be sometime before the end of the year but there's issues with clock skew that I think the devs are trying to fix first.

441357546

@441357546

@quentinw91 I am blocked... I try to write a tcl as following

441357546

@441357546

@quentinw91

read_lef "sky130/sky130_tech.lef"
read_lef "sky130/sky130.lef"
read_liberty "sky130/sky130_tt.lib"
//read_def "mydef.def"
//read_sdc "mysdc.sdc"

configure_cts_characterization     -max_cap cap 52 \
                                -max_slew slew 24 \
                                -sqr_cap capvalue 5 \
                                -sqr_res resvalue 5 \
                                -slew_inter slewvalue 8 \
                                -cap_inter capvalue 22

clock_tree_synthesis -buf_list <list_of_buffers> \
                      -out_path path ./sky130 \
                      -characterization_only 



write_def "final.def

But it come out a err named:

#Error: trygenerate.tcl, 12 invalid command name "configure_cts_characterization"

I try the following .tcl,it still failed.

read_lef "sky130/sky130_tech.lef"
read_lef "sky130/sky130.lef"
read_liberty "sky130/sky130_tt.lib"
//read_def "mydef.def"
//read_sdc "mysdc.sdc"



clock_tree_synthesis -buf_list <list_of_buffers> \
                      -out_path path ./sky130 \
                      -characterization_only \
             -max_cap cap 52 \
                                -max_slew slew 24 \
                                -sqr_cap capvalue 5 \
                                -sqr_res resvalue 5 \
                                -slew_inter slewvalue 8 \
                                -cap_inter capvalue 22



write_def "final.def

#Error: trygenerate.tcl, 16 TypeError in method 'TritonCTSKernel_set_max_char_cap', argument 2 of type 'double'

So I still confuse about generate those files(.lut and .sol_list), I wonder if you can give me a complete .tcl for reference,I would be very appreciate .

4 replies

jtpedicone

@jtpedicone

According to the Black Parrot article (https://cseweb.ucsd.edu/~mbtaylor/papers/BlackParrot_IEEE_Micro_2020.pdf) GF-12 was used for the libraries. We have access to the GF12 libraries so we can get most of the files needed to add a GF 12 platform. What we don't have are the .lyp, .lyt and the .lydrc files. Is there a repository where we can get these files or some way to run a program to create them?

Austin Rovinski

@rovinski

@jtpedicone NDAs with any major fab prevent the sharing of any proprietary details. You'll have to create those files on your own. .lyp is a layout properties file and is just convenient for viewing layouts, it isn't a required file. .lyt can be created by looking at a GDS mapping file provided by the kit. Creating a .lydrc is not reasonable for GF12. There are too many rules, which are probably too complex for any current open-source DRC engine to handle. You should use a commercial DRC engine at this time instead.

@441357546 you probably need to update your openroad version

shinku4lyfe

@shinku4lyfe_twitter

Hi, I've successfully installed openroadflow and can run make for the gcd default, but when I attempted to run another design black parrot get the error shown below. any help would be appreciated.

Austin Rovinski

@rovinski

@shinku4lyfe_twitter your system ran out of memory. If you are trying to run on a machine that only has 4 GB of RAM, you will need much more for larger designs. Possibly 20-30 GB.

shinku4lyfe

@shinku4lyfe_twitter

@rovinski Thanks a lot!

ayewinoung

@ayewinoung

Hi, looking to find a way to preserve RTL flip flop names through yosys synthesis and STA, so I can explore how I can fix critical paths ? Any suggestion on how to do that ? some level of "name" preservation would be very use full. Any switches in yosys write_verilog ? Thanks in advance !

3 replies

jtpedicone

@jtpedicone

When I try running fastroute with the sample gcd design, I get the following:

fastroute -guide_file ./results/gf12/gcd/route.guide -verbose 2
0:06.58elapsed 99%CPU 259360memKB
make: * [results/gf12/gcd/route.guide] Error 11

When I run in openroad interactively I see this:

[INFO] P3 runtime: 0.000000 sec
[INFO] Final 2D results:
[Overflow Report] total Usage : 4072
[Overflow Report] Max H Overflow: 0
[Overflow Report] Max V Overflow: 0
[Overflow Report] Max Overflow : 0
[Overflow Report] Num Overflow e: 0
[Overflow Report] H Overflow : 0
[Overflow Report] V Overflow : 0
[Overflow Report] Final Overflow: 0

Layer Assignment Begins
Layer assignment finished
[INFO] 2D + Layer Assignment Runtime: 4.210000 sec
Post Processing Begins
Error: heap underflow
Segmentation fault

Any suggestions?

4 replies

jtpedicone

@jtpedicone

When I run TritonRoute with the gcd design, I get the following errors when route.guide is read:

Warning: req_msg[12] 2 pin not visited, fall back to feedrough mode
Error: req_msg[12] 2 pin not visited #guides = 21
Error: critical error guide not connected, exit now 1!

jtpedicone

@jtpedicone

When I deleted the problem route guides from my 20:22 post, I was able to eliminate the previous errors. Now I get: Error: genGuides_split lineIdx is empty on M2. Any ideas on what this may be?

Austin Rovinski

@rovinski

@jtpedicone It's really hard to diagnose these problems from error messages alone. I would visually inspect the guides and routes for the problematic net to see if something looks suspicious. In OpenROAD-flow you can use make klayout_guides to view guides in KLayout or use make gui_final to view in the OpenROAD GUI. In either case you will have to adjust the Makefile to use the DEF for 4_cts.def rather than 5_route.def.

Your issue might have to do with cells with difficult pin access. (it is strongly recommended to put cells with strength less than X1 in DONT_USE_CELLS). Congestion might also be high, or if there are macros then the channel width might be too narrow / the keep-out halos aren't large enough.

7 replies

Pratik Shrestha

@prtx

Hello
Is this an appropriate channel to ask questions on OpenDB API?

Austin Rovinski

@rovinski

Sure. I may not have an answer, but I can try.

Pratik Shrestha

@prtx

Hi @rovinski
Im trying to load DEF files into OpenDB API and to some analyses and looking around for some documentation on the models. The github page says documentation is still being worked on. Is there any version available somewhere that I can work with? For starters Im trying to get the logical operations out of each gate instances in the design.

Matt Liberty

@maliberty

Lef & def don't deal with logical operations. You would find those in a .lib file and would have to access them through OpenSTA.

Pratik Shrestha

@prtx

Hi @maliberty
Thanks. I should definitely check OpenSTA too.
Im guessing OpenDB might have something related with what standard cell (eg. INV_X1, AND2_X1... in nangate45) each net in the design is. I can see them in the DEF file but tracking them in the API might be a bit challenging

Matt Liberty

@maliberty

@prtx I suggest you look at the unit tests for some examples https://github.com/The-OpenROAD-Project/OpenDB/tree/master/tests/tcl

1 reply

promach

@promach

do OpenROAD have predefined lego hardware such as negative and positive latch, OR gate, AND gate, inverter ?

I am trying to build this clock gating cell : https://electronics.stackexchange.com/questions/532665/questions-about-a-look-ahead-clock-gating-based-on-auto-gated-flip-flops

promach

@promach

Someone told me they could be located at https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_fd_sc_hd.git/+/refs/heads/master/cells/ , but which is negative latch ? which is positive latch ?

Matt Liberty

@maliberty

@promach skywater questions are best directed their slack channel. See https://invite.skywater.tools/ . You can always look at the .lib for the function of a cell if you have it.

quentinw91

@quentinw91

Hi, I am getting this warning, not sure what it means:

logs/5_2_TritonRoute.log:32:Warning: METAL1 does not have viaDef align with layer direction, generating new viaDef VIA12_FR...

My VIAs are perfectly square (so i should not need to define a prefered direction), yet it defines these new VIAs "_FR" and even uses them in the DEF. Is there an explanation about this ?

4 replies

samli50801

@samli50801

Hi, I would like to know what lut.txt and sol_list.txt are doing and how can i generate them by myself. Is there any document??

4 replies

Painting

@redpanda3

Anyone successfully deployed the openroad cloud?

ayeung-fw

@ayeung-fw

Hi, we have a test case where standard cells are placed over memories. Just wondering if anyone has come across something similar before.

ayeung-fw

@ayeung-fw

Another question I have is does Fastroute automatically time out? We are seeing the tool exit after 25 hours in a large test case.

ayeung-fw

@ayeung-fw

Hi, we have a test case where standard cells are placed over memories. Just wondering if anyone has come across something similar before.

"detailed_placement -max_displacement" does not work for me.

Matt Liberty

@maliberty

@ayeung-fw FR doesn't timeout. Perhaps it crashed? Are you seeing cells over a memory after global placement or detailed placement?

juspertor

@juspertor

Hi,

I found some issues in OpenRoad dealing with file-paths containing a space character. These issues can be fixed by changing 4 lines of code in 3 files:

file: src/OpenRoad.tcl

change line 49 from
set filename [file nativename $args]
to
set filename [lindex [file nativename $args] 0]

change line
set filename [file nativename $args]
to
set filename [lindex [file nativename $args] 0]

file: src/pdngen/src/PdnGen.tcl

change line 95 from
set config_file $args
to
set config_file [lindex $args 0]

file: src/OpenSTA/tcl/Liberty.tcl
change line 29 from
set filename [file nativename $args]
to
set filename [lindex [file nativename $args] 0]

ayeung-fw

@ayeung-fw

@maliberty FR always terminated after 25 hours, which looks like a time out to me but it may not be the case. We are seeing standard cells over big macros after detailed placement. In one test case, the problem went away after we split the memories into smaller ones. In another, we noticed the illegally placed cells were repeaters inserted during CTS.

Is there a way to modify the max_displacement (or max_displacment) value for -detailed_placement so the placer is allowed to move cells across a greater distance?

juspertor

@juspertor

Does anyone run yosys on Windows subsystem for Linux (wsl)? I use Ubuntu 18.04 on a Windows system and the execution terminates at step at "5.1.1. Executing ABC.ERROR: Can't open ABC output file `/tmp/yosys-abc-ihYbSB/output.blif'. " The same binaries and verilog file on a native Ubuntu18.04 system run fine. Also, all following steps of a full openroad flow run in the same way on wsl as on a native Ubuntu system. Just abc fails.

Matt Liberty

@maliberty

@juspertor how does using lindex help with special characters? It seems like it would cut off part of the file name. In any case specific fixes are best submitted as an issue or PR on github.

juspertor

@juspertor

$args is a list with one element in that case and the subsequent [file exists $filename] always returns false in that case for a list. So nothing is cut off. The solution with lindex is already used for read_sdc.

Matt Liberty

@maliberty

@juspertor I can run yosys on WSL.

promach

@promach

Hi, may I know if openROAD supports any MCMM (multi-mode, multi-corner) features ?

3 replies

Austin Rovinski

@rovinski

It depends on what you mean by file size. The source repo is ~1GB after recursive cloning. The build directory is ~150MB.

ayewinoung

@ayewinoung

OpenSTA not able to read output verilog file from yosys

yosys output verilog netlist of type "assign {a , b, c} = {x, y, z}" which is totally legal and correct. However, when OpenSTA read the netlist with "read_verilog", got error "Error: /verilog_fileName.v, line <lineNo> syntax error, unexpected '{', expecting ID.". Looks like I'm missing a trick in either writing out yosys verilog options or reading in from openSTA. Any help appreciated ? thanks.

juspertor

@juspertor

@ayewinoung
a splitnets command in yosys before writing the verilog is the trick. It will avoid not supported assign.

ayewinoung

@ayewinoung

@juspertor Awesome ! thanks, missed that part. Happy new year !

ayewinoung

@ayewinoung

Is there yosys command/settings/methodology to "stop" merge two sets of flip flops ? Got specific sets of flip flops I don't want yosys/abc to merge, they are identical, so ideal flops to merge. But I need to keep them two independent sets, so the design can scale well. Any thoughts, pointers appreciated ? thanks

2 replies

ayewinoung

@ayewinoung

Anyone try to bring up asap7 standard cell libs with OpenRoad flow ? Manged to do synthesis with Yosys, after a bit of fiddling with .lib files. I'm stucked with OpenSTA not being able to read .lib files with error "Warning: <libFile>, line <xxx> table template delay_template_7x7_x1 not found." and "Warning: <libFile>, line <xxx> table template power_template_7x7_x1 not found."

1 reply

OpenSTA wont find any timing path after that !

Glenn Ramalho

@glennramalho

I was wondering if there are any comparisons between OpenRoad and the commercial flows. I am looking at a potential analog device with a midsize digital block, perhaps not enough to justify paying 100K+ for tools to be used once. I believe it would be 180nm under 100K nand equivalent, low speed (under 5MHz). Do you think OpenRoad is at a stage it could be used reliably to build the digital part? Or would it make something so much bigger than a commercial tool would that it would not be worth it? I guess there is no LEC (logic equivalency checking) tool or DfT tool either, right?

2 replies

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