deleteNonClkNets.tclwhich produces a DEF that only has clock nets in it. You can run the script with
make gallerywhich creates several layout screenshots representing different design steps.
@tnt_twitter nope, not really. The only tool that really uses the wire API is pdngen. The API for TCL and Python is the same, it is generated from Swig. Although tcl has wrapper procs to do error checking so not exactly the same.
I think we're aiming to start concerted documentation efforts within a few months but I'm not sure. Your best bet until then is looking through header files.
set_driving_cellin your SDC to give it a better idea of the port input drive. If you really don't want resizer touching the buffers, then you can set the buffer placement status to
FIXEDand I believe that will prevent resizer from touching it.