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    Austin Rovinski
    @rovinski

    How to force the cells track, not the metals track ?
    Laurent

    @laurentc2 I'm not sure what you're asking, can you elaborate?

    2 replies
    Austin Rovinski
    @rovinski
    @quentinw91 Internal error is basically an assertion failure, i.e. a bug. If you can provide a detailed test case to OpenSTA, I would do so.
    Cheng Tan
    @tancheng
    @rovinski Hi Austin, I am new to OpenRoad. When I tried to place a new design, it showed the ERROR "RePlAce divergence detected. Please decrease init_density_penalty value (REPL-3)". I saw you replied to @gkamendje_gitlab that we need to make the DENSITY higher than the CORE_UTILIZATION, and I did do that (you can see util(%)=24.613287 and TargetDensity=0.2500). Do you have any idea about this error? The screenshot is as follows.
    Notice 0: Finished DEF file: ./results/nangate45/comp/2_floorplan.def
    [INFO] DBU = 2000
    [INFO] SiteSize = (380, 2800)
    [INFO] CoreAreaLxLy = (20140, 22400)
    [INFO] CoreAreaUxUy = (140220, 140000)
    [INFO] NumInstances = 491
    [INFO] NumPlaceInstances = 407
    [INFO] NumFixedInstances = 84
    [INFO] NumDummyInstances = 0
    [INFO] NumNets = 615
    [INFO] NumPins = 1653
    [INFO] DieAreaLxLy = (0, 0)
    [INFO] DieAreaUxUy = (160340, 160000)
    [INFO] CoreAreaLxLy = (20140, 22400)
    [INFO] CoreAreaUxUy = (140220, 140000)
    [INFO] CoreArea = 14121408000
    [INFO] NonPlaceInstsArea = 89376000
    [INFO] PlaceInstsArea = 3453744000
    [INFO] Util(%) = 24.613287
    [INFO] StdInstsArea = 3453744000
    [INFO] MacroInstsArea = 0
    [InitialPlace]  Iter: 1 CG Error: 8.22656e-08 HPWL: 43844280
    [InitialPlace]  Iter: 2 CG Error: 1.18405e-06 HPWL: 25511121
    [InitialPlace]  Iter: 3 CG Error: 1.09402e-07 HPWL: 20147647
    [InitialPlace]  Iter: 4 CG Error: 9.91762e-08 HPWL: 19970488
    [InitialPlace]  Iter: 5 CG Error: 1.15753e-07 HPWL: 19917056
    [INFO] FillerInit: NumGCells = 413
    [INFO] FillerInit: NumGNets = 615
    [INFO] FillerInit: NumGPins = 1653
    [INFO] TargetDensity = 0.250000
    [INFO] AveragePlaceInstArea = 8485857
    [INFO] IdealBinArea = 33943428
    [INFO] IdealBinCnt = 416
    [INFO] TotalBinArea = 14121408000
    [INFO] BinCnt = (16, 16)
    [INFO] BinSize = (7505, 7350)
    [INFO] NumBins = 256
    [NesterovSolve] Iter: 1 overflow: 0.480216 HPWL: 23894010
    [ERROR] RePlAce divergence detected. 
            Please decrease init_density_penalty value (REPL-3)
    Error: RePlAce terminated with errors.
    Austin Rovinski
    @rovinski
    @tancheng 24.6% is still very close to 25%. Try setting place density to 30% and see if it helps.
    Cheng Tan
    @tancheng
    @rovinski Thanks Austin, I sweep from 1% to 100%. It does not work. when it is set more than 24.6%, it shows "please decrease", when it is set equal or less than 24.6%, it shows "please put higher target density"...
    Austin Rovinski
    @rovinski
    @tancheng Hmmm... Sometimes RePlAce can have problems with a design if it is very small. I see your design is <500 instances. Try adding export GLOBAL_PLACEMENT_ARGS = -skip_initial_place to your design config file.
    laurentc2
    @laurentc2
    I have tried to use : write_path_spice to generate a spice netlist for LVS.
    But I really cannot figure out what argument to pass to : -path_args
    I have even looked at the OpenSTA code and could find what is path_args.
    An example with write_path_spice would be welcome.
    Austin Rovinski
    @rovinski
    @laurentc2 Maybe I'm mistaken but I don't think OpenSTA is meant to output spice for LVS... it's more for netlist simulation.
    Our workflow is to take the final verilog netlist using write_verilog and convert it to spice / CDL. Yosys can do this.
    Also if you're curious, OpenSTA has PDF documentation in OpenSTA/doc/OpenSTA.pdf
    laurentc2
    @laurentc2
    @rovinski I see your flow. By the way, FreePDK45 already has the KLayout LVS script. It is currently manual, but it can easily be scripted.
    Austin Rovinski
    @rovinski
    Yes, we plan to make this part of the flow in the next update. We need to make the flow repository non read-only first.
    laurentc2
    @laurentc2
    @rovinski I just generated the spice netlist through that flow based on Yosys, and I see 2 drawbacks :
    • the library is never provided with the blackbox_library.v file, but with a CDL spice netlist, so the blackbox_library.v file has to be generated
    • the bus is generated as bus.0 bus.1 bus.2 ... while we need bus[0], bus[1], bus[2]... for the LVS
      The spice netlist generated from OpenSTA for the NGSPICE simulations is from a CDL spice netlist of a libray. So modifying it for the spice netlist for the LVS would be easier for a new library.
      It was just my hint ...
    quentinw91
    @quentinw91
    Hi, i build openroad_flow_public, everything looks to be ok, but i cannot start openroad:
    openroad: error while loading shared libraries: libQt5Widgets.so.5: cannot open shared object file: No such file or directory
    I tried with --latest option to build_openroad.sh, same thing
    Austin Rovinski
    @rovinski
    @quentinw91 openroad-flow-public is not compatible with the latest version of OpenROAD.
    For this specific issue you can add RUN yum install -y qt5-qtbase-devel into openroad-flow-public/Dockerfile
    2 replies
    arelysn
    @arelysn
    image.png
    Hi, someone previously posted an issue like this one but i couldn't find the resolution. I've successfully installed openroadflow and can run make for the gcd default. when attempting to run on my own file i get the error shown below. any help would be appreciated.
    quentinw91
    @quentinw91
    @arelysn i think it is because you have given a CORE AREA too small in your config file. Because of this, the PDN does not have enough room to create the power rails (and bombs this weird error because it cannot find the rail location after). you should increase the core area or redefine the power rail defintion (defined in platforms/$(PLATFORM)/pdn.cfg) to fit your design
    1 reply
    Matt Liberty
    @maliberty
    @arelysn if you can provide a test case it would be good to file an issue on the openroad github
    1 reply
    jtpedicone
    @jtpedicone

    I'm trying to install OpenROAD. When I try to build it, I get a fatal Python error:

    ./build_openroad.sh --local
    [INFO][FLOW-0000] using local build method. This will create binaries at tools/build/
    Fatal Python error: initfsencoding: Unable to get the locale encoding
    ModuleNotFoundError: No module named 'encodings'

    My HOSTTYPE is x86_64-linux and I'm using python-3.7.0.

    Any ideas on how to fix this?

    2 replies
    Ukuer
    @Ukuer_gitlab
    Hi @quentinw91 i had a same problem as you. There is a solution: run yum install qt5-qtbase in docker : )
    Ukuer
    @Ukuer_gitlab
    Hello everyone! i am new to OpenROAD and i want to have a code analysis for OpenROAD, but i have no idea where i should begin. Can somebody give me a suggestion? : )
    ayeung-fw
    @ayeung-fw
    Hi, I would like to find out if there is some way to control the number of iterations run in TritonRoute. I don't think the parameter "timeout:2400" is being honored as well.
    Austin Rovinski
    @rovinski
    @ayeung-fw TritonRoute iterations are not really user-controllable. It continues to iterate while design rule violations exist, or it hits a predefined limit in the code (I think currently it's about 60-70). I think the timeout parameter is no longer supported. (when it was supported, it would simply exit the program once the time threshold was hit)
    ayeung-fw
    @ayeung-fw
    @rovinski Thanks for your reply!
    ayewinoung
    @ayewinoung
    @here - looking for help with install, new to openroad, follow user Guide and mange to install and compile yosys & TritonRoute. But when try to build the flow with "build_openroad.sh", got following error. "lemon" is installed in /usr/bin

    [INFO][FLOW-0000] using local build method. This will create binaries at tools/build/
    [Makefile.conf] CONFIG := clang
    mkdir -p ../build/yosys/bin
    cp yosys yosys-config yosys-abc yosys-filterlib yosys-smtbmc ../build/yosys/bin
    strip -S ../build/yosys/bin/yosys
    strip ../build/yosys/bin/yosys-abc
    strip ../build/yosys/bin/yosys-filterlib
    mkdir -p ../build/yosys/share/yosys
    cp -r share/. ../build/yosys/share/yosys/.
    -- leflib_home: /mnt/tools/OpenRoad/OpenROAD-flow/tools/TritonRoute/module/lef/5.8-p029
    -- Configuring done
    -- Generating done
    -- Build files have been written to: /mnt/tools/OpenRoad/OpenROAD-flow/tools/build/TritonRoute
    [ 1%] Built target DefBisonTarget
    [ 1%] Built target LefBisonTarget
    [ 40%] Built target lef
    [ 54%] Built target def
    [ 56%] Built target lefzlib
    [ 58%] Built target defzlib
    [100%] Built target TritonRoute
    -- OpenROAD version: 0.9.0
    -- OpenROAD git sha: 16d3aca673ed5ac40a9e04dd3788d7205dcffb5c
    -- System name: Linux
    -- Compiler: Clang 11.0.0
    -- Build type: RELEASE
    -- Install prefix: /usr/local
    -- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
    -- TCL header: /usr/include/tcl/tcl.h
    -- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
    -- TCL header: /usr/include/tcl/tcl.h
    -- leflib_home: /mnt/tools/OpenRoad/OpenROAD-flow/tools/OpenROAD/src/OpenDB/src/lef
    -- Could NOT find Doxygen (missing: DOXYGEN_EXECUTABLE)
    -- STA version: 2.2.0
    -- STA git sha: 0d73b5b65a185329ea77478d4670d8a103b0b710
    -- System name: Linux
    -- Compiler: Clang 11.0.0
    -- Build type: RELEASE
    -- Build CXX_FLAGS: -O3 -DNDEBUG
    -- Install prefix: /usr/local
    -- TCL library: /usr/lib/x86_64-linux-gnu/libtcl.so
    -- TCL header: /usr/include/tcl/tcl.h
    -- CUDD library: not found
    -- SSTA: 0
    -- STA executable: /mnt/tools/OpenRoad/OpenROAD-flow/tools/OpenROAD/src/OpenSTA/app/sta
    CMake Error at src/TritonCTS/src/CMakeLists.txt:44 (find_package):
    By not providing "FindLEMON.cmake" in CMAKE_MODULE_PATH this project has
    asked CMake to find a package configuration file provided by "LEMON", but
    CMake did not find one.

    Could not find a package configuration file provided by "LEMON" with any of
    the following names:

    LEMONConfig.cmake
    lemon-config.cmake

    Add the installation prefix of "LEMON" to CMAKE_PREFIX_PATH or set
    "LEMON_DIR" to a directory containing one of the above files. If "LEMON"
    provides a separate development package or SDK, be sure it has been
    installed.

    -- Configuring incomplete, errors occurred!
    See also "/mnt/tools/OpenRoad/OpenROAD-flow/tools/build/OpenROAD/CMakeFiles/CMakeOutput.log".
    See also "/mnt/tools/OpenRoad/OpenROAD-flow/tools/build/OpenROAD/CMakeFiles/CMakeError.log".

    Matt Liberty
    @maliberty
    Lemon is a graph library. There is a totally unrelated package lemon package that is a parser generator. I suspect you have the other one since you mention it is a binary.

    See the Dockerfile:

    lemon required by TritonCTS (no package for CentOS!)

    (On Ubuntu liblemon-dev can be used instead)

    RUN wget http://lemon.cs.elte.hu/pub/sources/lemon-1.3.1.tar.gz \
    && tar -xf lemon-1.3.1.tar.gz \
    && cd lemon-1.3.1 \
    && cmake -B build . \
    && cmake --build build -j $(nproc) --target install

    ayewinoung
    @ayewinoung
    @maliberty make sense, I'll try to get that, thanks.
    441357546
    @441357546
    Hello everyone!I am new to OpenROAD and I am glad to join this.But I am runing into trouble in TrainCTS at OpenROAD.I found there are some file named (filename).lut and (filename).sol_list, if someone can teach me how to create or generate those file,I will be very appreciate
    quentinw91
    @quentinw91

    @441357546 The TritonCTS README (https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/TritonCTS/README.md) explains the parameters you can set. But it has not been updated with recent changes. You should use configure_cts_characterization before calling clock_tree_synthesis if you do not have the lut and sol_list files, see:

    #Clock Tree Synthesis TCL -> Required commands:
    #                               clock_tree_synthesis -lut_file , -sol_list , -root-buf, -wire_unit
    #                                               or
    #                               configure_cts_characterization -sqr_cap , -sqr_res + clock_tree_synthesis -buf_list

    (found in https://github.com/The-OpenROAD-Project/OpenROAD/blob/master/src/TritonCTS/src/tritoncts.tcl)

    441357546
    @441357546
    @quentinw91 Appreciate for your help, I just read the TritonCTS README. But I sill had some confuse,for exampl ,if I run this file inhttps://github.com/The-OpenROAD-Project/OpenROAD/tree/master/test/sky130with start aes_sky130.tcl,what shoud i do if i lost the .lut and .sol_list files, can we generate those files.
    quentinw91
    @quentinw91
    you can write a simple tcl script like the following to have openroad generating the files. By specifying -out_path, clock_tree_synthesis will save the generated characiterization files (.lut and .solt_list) in the given path:
    read_lef "sky130_tech.lef"
    read_lef "sky130_std_cell.lef"
    read_liberty "sky130_tt.lib"
    read_def "mydef.def"
    read_sdc "mysdc.sdc"
    
    configure_cts_characterization     [-max_cap cap] \
                                    [-max_slew slew] \
                                    [-sqr_cap capvalue] \
                                    [-sqr_res resvalue] \
                                    [-slew_inter slewvalue] \
                                    [-cap_inter capvalue]
    
    clock_tree_synthesis -buf_list <list_of_buffers> \
                          [-out_path path] \
                          [-characterization_only] \
    
    write_def "final.def"
    441357546
    @441357546
    @quentinw91 Appreciate for your help,i will try it later.Thanks !! i will tell u if i get advance.
    Austin Rovinski
    @rovinski
    Manual CTS characterization is supposed to eventually go away in favor of automatic characterization... but I still don't know when that's supposed to happen. I was hoping it was going to be sometime before the end of the year but there's issues with clock skew that I think the devs are trying to fix first.
    441357546
    @441357546
    @quentinw91 I am blocked... I try to write a tcl as following
    441357546
    @441357546

    @quentinw91

    read_lef "sky130/sky130_tech.lef"
    read_lef "sky130/sky130.lef"
    read_liberty "sky130/sky130_tt.lib"
    //read_def "mydef.def"
    //read_sdc "mysdc.sdc"
    
    configure_cts_characterization     -max_cap cap 52 \
                                    -max_slew slew 24 \
                                    -sqr_cap capvalue 5 \
                                    -sqr_res resvalue 5 \
                                    -slew_inter slewvalue 8 \
                                    -cap_inter capvalue 22
    
    clock_tree_synthesis -buf_list <list_of_buffers> \
                          -out_path path ./sky130 \
                          -characterization_only 
    
    
    
    write_def "final.def

    But it come out a err named:

    #Error: trygenerate.tcl, 12 invalid command name "configure_cts_characterization"

    I try the following .tcl,it still failed.

    read_lef "sky130/sky130_tech.lef"
    read_lef "sky130/sky130.lef"
    read_liberty "sky130/sky130_tt.lib"
    //read_def "mydef.def"
    //read_sdc "mysdc.sdc"
    
    
    
    clock_tree_synthesis -buf_list <list_of_buffers> \
                          -out_path path ./sky130 \
                          -characterization_only \
                 -max_cap cap 52 \
                                    -max_slew slew 24 \
                                    -sqr_cap capvalue 5 \
                                    -sqr_res resvalue 5 \
                                    -slew_inter slewvalue 8 \
                                    -cap_inter capvalue 22
    
    
    
    write_def "final.def
    #Error: trygenerate.tcl, 16 TypeError in method 'TritonCTSKernel_set_max_char_cap', argument 2 of type 'double'

    So I still confuse about generate those files(.lut and .sol_list), I wonder if you can give me a complete .tcl for reference,I would be very appreciate .

    4 replies
    jtpedicone
    @jtpedicone
    According to the Black Parrot article (https://cseweb.ucsd.edu/~mbtaylor/papers/BlackParrot_IEEE_Micro_2020.pdf) GF-12 was used for the libraries. We have access to the GF12 libraries so we can get most of the files needed to add a GF 12 platform. What we don't have are the .lyp, .lyt and the .lydrc files. Is there a repository where we can get these files or some way to run a program to create them?
    Austin Rovinski
    @rovinski
    @jtpedicone NDAs with any major fab prevent the sharing of any proprietary details. You'll have to create those files on your own. .lyp is a layout properties file and is just convenient for viewing layouts, it isn't a required file. .lyt can be created by looking at a GDS mapping file provided by the kit. Creating a .lydrc is not reasonable for GF12. There are too many rules, which are probably too complex for any current open-source DRC engine to handle. You should use a commercial DRC engine at this time instead.
    @441357546 you probably need to update your openroad version
    shinku4lyfe
    @shinku4lyfe_twitter
    image.png
    Hi, I've successfully installed openroadflow and can run make for the gcd default, but when I attempted to run another design black parrot get the error shown below. any help would be appreciated.
    Austin Rovinski
    @rovinski
    @shinku4lyfe_twitter your system ran out of memory. If you are trying to run on a machine that only has 4 GB of RAM, you will need much more for larger designs. Possibly 20-30 GB.
    shinku4lyfe
    @shinku4lyfe_twitter
    @rovinski Thanks a lot!
    ayewinoung
    @ayewinoung
    Hi, looking to find a way to preserve RTL flip flop names through yosys synthesis and STA, so I can explore how I can fix critical paths ? Any suggestion on how to do that ? some level of "name" preservation would be very use full. Any switches in yosys write_verilog ? Thanks in advance !
    3 replies
    jtpedicone
    @jtpedicone

    When I try running fastroute with the sample gcd design, I get the following:

    fastroute -guide_file ./results/gf12/gcd/route.guide -verbose 2
    0:06.58elapsed 99%CPU 259360memKB
    make: * [results/gf12/gcd
    /route.guide] Error 11

    When I run in openroad interactively I see this:

    [INFO] P3 runtime: 0.000000 sec
    [INFO] Final 2D results:
    [Overflow Report] total Usage : 4072
    [Overflow Report] Max H Overflow: 0
    [Overflow Report] Max V Overflow: 0
    [Overflow Report] Max Overflow : 0
    [Overflow Report] Num Overflow e: 0
    [Overflow Report] H Overflow : 0
    [Overflow Report] V Overflow : 0
    [Overflow Report] Final Overflow: 0

    Layer Assignment Begins
    Layer assignment finished
    [INFO] 2D + Layer Assignment Runtime: 4.210000 sec
    Post Processing Begins
    Error: heap underflow
    Segmentation fault

    Any suggestions?

    4 replies
    jtpedicone
    @jtpedicone

    When I run TritonRoute with the gcd design, I get the following errors when route.guide is read:

    Warning: req_msg[12] 2 pin not visited, fall back to feedrough mode
    Error: req_msg[12] 2 pin not visited #guides = 21
    Error: critical error guide not connected, exit now 1!

    jtpedicone
    @jtpedicone
    When I deleted the problem route guides from my 20:22 post, I was able to eliminate the previous errors. Now I get: Error: genGuides_split lineIdx is empty on M2. Any ideas on what this may be?
    Austin Rovinski
    @rovinski

    @jtpedicone It's really hard to diagnose these problems from error messages alone. I would visually inspect the guides and routes for the problematic net to see if something looks suspicious. In OpenROAD-flow you can use make klayout_guides to view guides in KLayout or use make gui_final to view in the OpenROAD GUI. In either case you will have to adjust the Makefile to use the DEF for 4_cts.def rather than 5_route.def.

    Your issue might have to do with cells with difficult pin access. (it is strongly recommended to put cells with strength less than X1 in DONT_USE_CELLS). Congestion might also be high, or if there are macros then the channel width might be too narrow / the keep-out halos aren't large enough.

    7 replies
    Pratik Shrestha
    @prtx
    Hello
    Is this an appropriate channel to ask questions on OpenDB API?