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Activity
  • 17:22

    mzabeltud on v1.1.2-Vivado

    ZTEX204, ARTY35+100T, NEXYS4DDR… Merge remote-tracking branch 'g… (compare)

  • 17:03

    mzabeltud on v1.1.2

    ZTEX204, ARTY35+100T, NEXYS4DDR… (compare)

  • Sep 14 14:56
    mbieker opened #67
  • Aug 26 02:39
  • Aug 18 07:56
  • Aug 16 17:08

    mzabeltud on v1.1.2-Vivado

    Added mig_ZTEX204_XC6SLX16_DDR. Fixed mig_ZTEX204_XC6SLX16_DDR. Removed unused logic in mem.tim… and 1 more (compare)

  • Aug 16 16:22

    mzabeltud on v1.1.2

    Removed unused logic in mem.tim… (compare)

  • Aug 16 14:34

    mzabeltud on v1.1.2

    Fixed mig_ZTEX204_XC6SLX16_DDR. (compare)

  • Aug 16 14:17

    mzabeltud on v1.1.2

    Added mig_ZTEX204_XC6SLX16_DDR. (compare)

  • Aug 14 19:51

    mzabeltud on v1.1.2-Vivado

    Added board QM_XC6SLX16_DDR3 Added MIG DDR3 controller for Q… Added board QM_XC6SLX16_SDRAM and 11 more (compare)

  • Aug 13 04:08
  • Aug 12 19:46

    mzabeltud on v1.1.2

    Added entity PoC.mem_timeslice_… (compare)

  • Aug 11 19:47

    mzabeltud on v1.1.2

    Fixed timings for SDRAM Control… (compare)

  • Aug 07 21:52
  • Jul 19 13:39
  • Jul 16 02:25
  • Jun 20 18:27
    Divyanirankari edited #66
  • Jun 20 18:26
    Divyanirankari edited #66
  • Jun 20 18:25
    Divyanirankari opened #66
  • Jun 17 19:58
    Peppar commented #62
Patrick Lehmann
@Paebbels
Welcome to this new news room.