Paebbels on master
Whitespace cleanup. Added new ClockNetwork componen… Added more config files for com… and 2 more (compare)
mzabeltud on v1.1.2
Fixed line endigns. (compare)
my_config.vhdlper project. It is shared in the parent repository.
my_project.vhdlis specific to each machine and not intended to be shared with Git.
@qarlosalberto Yes, he will publish the code, when his thesis is in the review phase. I know, we'll annoy a lot of IP core vendors, but on the other side, why do the offer a so simple IP core for ~15,000 €? yes......
/debug/fifo_ic_got.vhd:293:35: can't resolve overload for function call, slice or indexed name /debug/fifo_ic_got.vhd:293:35: possible interpretations are: ../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned" ../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"
vu.set_compile_option('ghdl.a_flags', ['--ieee=synopsys', '-frelaxed-rules']). Some of the widely used, accepted styles, aren't technically compliant with the VHDL LRM. GHDL is much more strictly compliant to the LRM whereas many commercial simulators have default settings to de-escalate these LRM compliance issues as info/warnings simply because so many people use the non-standard IEEE libraries and those code styles. GHDL has the above flags to overcome these problems. I usually add the following line as well for simulation
vu.set_sim_option('ghdl.elab_flags', ['--ieee=synopsys', '-frelaxed-rules'])
Also, make sure you're using the latest stable release and check their CI commands to see how they simulate with GHDL. Last time I checked, PoC uses GHDL for simulation so I know their code will work with that simulator