IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
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The PoC-Library - Service Tool
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Initializing PoC-Library Service Tool for synthesis
FATAL: An unknown or unhandled exception reached the topmost exception handler!
Exception type: AttributeError
Exception message: 'Namespace' object has no attribute 'Dependencies'
but sync_bits_xilinx
@Paebbels Actually I may want sync_strobe or pulse, as it's a clk input varying from 0 to 600khz
though 600kHz doesn't sound that fast in terms of FPGAs
Hi @Paebbels,
maybe it's a dumb question, but have you aver thought about splitting up the PoC Library into two parts, a top level wrapper with python scripts and a hdl only library as a submodule? These two projects could be developed independently, and it would be easier to include the hdl library as a submodule in other projects.
maybe it's a dumb question, but have you aver thought about splitting up the PoC Library into two parts, a top level wrapper with python scripts and a hdl only library as a submodule? These two projects could be developed independently, and it would be easier to include the hdl library as a submodule in other projects.
Hello @FranzForstmayr,
with PoC v1.2.0 (and 1.2.0-Vivado) - 8 days ago, PoC was split into:
with PoC v1.2.0 (and 1.2.0-Vivado) - 8 days ago, PoC was split into:
- "VHDL code" + pyIPCMI description files (in
.pyIPCMI), and - the submodule pyIPCMI in
lib/pyIPCMI.
I also have received a list of improvements, which I'm currently reviewing. But I thought the split was more important and may need some further fixes which I can deliver with the reviewed data.
Maybe there's also a nice way to replace PoC/src/common/my_project.vhdl files, because the file path is always specific for a given project. Same for my_config.vhdl when writing a generic module.
PoC has 3 use cases, have you reviewed them on ReadTheDocs?
- stand alone - zip
- stand alone - Git
- Git submodule
You should use the latter use case. Here you create one
my_config.vhdl per project. It is shared in the parent repository.
The
my_project.vhdl is specific to each machine and not intended to be shared with Git.
If you don't use write file and read file operations in synthesis, you can use dummy data in
my_project.vhdl
I'll double check the remaining issue, my last hdl project is already some month ago.
@qarlosalberto Yes, he will publish the code, when his thesis is in the review phase. I know, we'll annoy a lot of IP core vendors, but on the other side, why do the offer a so simple IP core for ~15,000 €?
:)
@qarlosalberto Yes, he will publish the code, when his thesis is in the review phase. I know, we'll annoy a lot of IP core vendors, but on the other side, why do the offer a so simple IP core for ~15,000 €? yes......
yesterday I saw a simple multiplier for only one use
XD
it was just an wrapper of the Xilinx macro
@leduchuybk There is no full list of IP cores, because it's over 120 IPs. When you open the IP core documentation of PoC on ReadTheDocs.org, you'll see the full list of cores in the navigation tree:
If you search a specific core, you can use the search bar and e.g. search for
pwm: https://poc-library.readthedocs.io/en/release/search.html?q=pwm&check_keywords=yes&area=default
If you can a specific question, you can also ask me here.
thank for your reply. i'm a undergraduated student searching for projects to strengthen my code skills. so may i ask for your current ip u guys developing. i want to learn and contribute to the project. besides, i can see all the ip doc written in german. anywhere i can find the english version.
who is interested in digital ic design?