VLSI-EDA/PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Patrick Lehmann

@Paebbels

Hello @Duckle29. What IP core are you using from PoC.misc.sync?

Mikkel Jeppesen

@Duckle29

@Paebbels At the moment I'm just trying to figure out how to use it, I'm entirely a novice

but sync_bits_xilinx

@Paebbels Actually I may want sync_strobe or pulse, as it's a clk input varying from 0 to 600khz

though 600kHz doesn't sound that fast in terms of FPGAs

FranzForstmayr

@FranzForstmayr

Hi @Paebbels,
maybe it's a dumb question, but have you aver thought about splitting up the PoC Library into two parts, a top level wrapper with python scripts and a hdl only library as a submodule? These two projects could be developed independently, and it would be easier to include the hdl library as a submodule in other projects.

Patrick Lehmann

@Paebbels

Hello @FranzForstmayr,
with PoC v1.2.0 (and 1.2.0-Vivado) - 8 days ago, PoC was split into:

"VHDL code" + pyIPCMI description files (in .pyIPCMI), and
the submodule pyIPCMI in lib/pyIPCMI.

Patrick Lehmann

@Paebbels

Currently, I have a new student working on:

a generic 10G/40G/100G Ethernet MAC (xgemac)
a generic 1/10/40/100G capable IP and UDP layer
adapters from 1/10/40/100G to 1G lowspeed protocols like
- ARP
- NDP
- ICMP

Patrick Lehmann

@Paebbels

If you like, please checkout the latest version and have a try if I made the split correct :). I'm currently checking if everything works as expected.

I also have received a list of improvements, which I'm currently reviewing. But I thought the split was more important and may need some further fixes which I can deliver with the reviewed data.

FranzForstmayr

@FranzForstmayr

ok, i have to look exactly at this changes. For some reason GitHub hides the 1.2 release at first sight. Is the PoC hdl part tightly coupled with your build scripts? Or could you imagine to create another abstraction layer between?

Patrick Lehmann

@Paebbels

The HDL part is not so tighly coupled. The file formats for the IP core database and descriptions might be the problematic part. Currently these formats are stable but might change in a newer release. Currently, I have planned a better parser but no new formats.

FranzForstmayr

@FranzForstmayr

Ok, i'm using a VUnit top wrapper and want to use the PoC library as a submodule. Maybe i can find a good way to include the PoC Library and automatically include vhdl files depending on their version (v08 and v93 issues).

Maybe there's also a nice way to replace PoC/src/common/my_project.vhdl files, because the file path is always specific for a given project. Same for my_config.vhdl when writing a generic module.

Patrick Lehmann

@Paebbels

PoC has 3 use cases, have you reviewed them on ReadTheDocs?

stand alone - zip
stand alone - Git
Git submodule

You should use the latter use case. Here you create one my_config.vhdl per project. It is shared in the parent repository.

The my_project.vhdl is specific to each machine and not intended to be shared with Git.

If you don't use write file and read file operations in synthesis, you can use dummy data in my_project.vhdl

FranzForstmayr

@FranzForstmayr

yeah, this is the part, where i want to use the VUnit Framework, it's easy to read and write files and verify them in python after simulation

I'll double check the remaining issue, my last hdl project is already some month ago.

Patrick Lehmann

@Paebbels

There is a branch on my machine, where I investigate how to integrate VUnit (to be specific: the VUnit runner) into PoC

Carlos Alberto Ruiz Naranjo

@qarlosalberto

@Paebbels is your student publishing the code?

Patrick Lehmann

@Paebbels

In a later stage, we might split the pyIPCMI repositories into more repositories:

EDA tool abstraction layer
File formats
...

@qarlosalberto Yes, he will publish the code, when his thesis is in the review phase. I know, we'll annoy a lot of IP core vendors, but on the other side, why do the offer a so simple IP core for ~15,000 €?

Carlos Alberto Ruiz Naranjo

@qarlosalberto

good! :=)

@qarlosalberto Yes, he will publish the code, when his thesis is in the review phase. I know, we'll annoy a lot of IP core vendors, but on the other side, why do the offer a so simple IP core for ~15,000 €? yes......

yesterday I saw a simple multiplier for only one use

it was just an wrapper of the Xilinx macro

leduchuybk

@leduchuybk

Hi i'm new to this project. As i read down the Docs. this seems to be a library of IP core like Xilinx's or Altera . But I couldnt find any full list of IP core u can provide. Thanks

Patrick Lehmann

@Paebbels

@leduchuybk There is no full list of IP cores, because it's over 120 IPs. When you open the IP core documentation of PoC on ReadTheDocs.org, you'll see the full list of cores in the navigation tree:

If you search a specific core, you can use the search bar and e.g. search for pwm: https://poc-library.readthedocs.io/en/release/search.html?q=pwm&check_keywords=yes&area=default

If you can a specific question, you can also ask me here.

leduchuybk

@leduchuybk

thank for your reply. i'm a undergraduated student searching for projects to strengthen my code skills. so may i ask for your current ip u guys developing. i want to learn and contribute to the project. besides, i can see all the ip doc written in german. anywhere i can find the english version.

Patrick Lehmann

@Paebbels

Hi, to what German documentation are you referring? I was hoping that we never released any Germany documentation, otherwise we would need to translate it :).

Jevin Sweval

@jevinskie

Any updates on VLSI-EDA/PoC#62 ? I’d really like to get started using PoC

Jevin Sweval

@jevinskie

I’ve managed to get around a few issues and now the .files parser is erroring out on the alu prng .file expecting an include token on the first character of the file (a # comment)

Arman Galstyan

@AGalstyanK622

Hi all

who is interested in digital ic design?

Jevin Sweval

@jevinskie

Me! Haven’t heard a peep from @all in here for a while though

Patrick Lehmann

@Paebbels

@jevinskie I'm working on a new release. The library has been used in some projects at my company and we'll now release some changes and additions.

Carlos Alberto Ruiz Naranjo

@qarlosalberto

Hi! I want to use the fifo in my project. I'm simulating it with VUnit and GHDL. I have this error:

/debug/fifo_ic_got.vhd:293:35: can't resolve overload for function call, slice or indexed name
/debug/fifo_ic_got.vhd:293:35: possible interpretations are:
../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned"
../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"

I'm trying to use only the the minimal files

GlenNicholls

@GlenNicholls

@qarlosalberto assuming you've configured PoC properly, this likely isn't an issue with GHDL or PoC. You probably aren't using the correct flags for GHDL

Try vu.set_compile_option('ghdl.a_flags', ['--ieee=synopsys', '-frelaxed-rules']). Some of the widely used, accepted styles, aren't technically compliant with the VHDL LRM. GHDL is much more strictly compliant to the LRM whereas many commercial simulators have default settings to de-escalate these LRM compliance issues as info/warnings simply because so many people use the non-standard IEEE libraries and those code styles. GHDL has the above flags to overcome these problems. I usually add the following line as well for simulation vu.set_sim_option('ghdl.elab_flags', ['--ieee=synopsys', '-frelaxed-rules'])

Also, make sure you're using the latest stable release and check their CI commands to see how they simulate with GHDL. Last time I checked, PoC uses GHDL for simulation so I know their code will work with that simulator

Carlos Alberto Ruiz Naranjo

@qarlosalberto

thank you @GlenNicholls !!!! :)

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