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  • Jun 20 18:27
    Divyanirankari edited #66
  • Jun 20 18:26
    Divyanirankari edited #66
  • Jun 20 18:25
    Divyanirankari opened #66
  • Jun 17 19:58
    Peppar commented #62
  • May 15 18:41
  • May 11 11:52
    oholimoli commented #62
  • May 04 20:38

    mzabeltud on v1.1.2

    Initial testbench for sdram_ctr… Fixed sdram_ctrl_fsm: burst len… (compare)

  • Apr 29 16:38

    mzabeltud on v1.1.2

    Extended sdram_mem2ctrl_adapter… (compare)

  • Apr 28 03:12
  • Apr 21 18:29

    mzabeltud on v1.1.2

    Used new PoC.sdram_mem2ctrl_ada… (compare)

  • Apr 21 18:28

    mzabeltud on v1.1.2

    New adapter between PoC.Mem and… (compare)

  • Apr 19 17:56

    mzabeltud on v1.1.2

    Fixed documentation of mem2mig … (compare)

  • Apr 19 16:29

    mzabeltud on v1.1.2

    Improved memtest example for QM… (compare)

  • Apr 19 16:26

    mzabeltud on v1.1.2

    Added byte write-enable for sdr… (compare)

  • Apr 16 06:58

    mzabeltud on v1.1.2

    Documented tested configuration… (compare)

  • Apr 11 09:19
  • Apr 02 13:07
  • Mar 27 07:27

    mzabeltud on v1.1.2

    Added memtest example for QMTEC… (compare)

  • Mar 27 07:05

    mzabeltud on v1.1.2

    Added board QM_XC6SLX16_SDRAM Added SDRAM Controller for QM X… (compare)

  • Mar 15 15:28

    mzabeltud on v1.1.2

    Added MIG DDR3 controller for Q… (compare)

Carlos Alberto Ruiz Naranjo
@qarlosalberto
:)
@qarlosalberto Yes, he will publish the code, when his thesis is in the review phase. I know, we'll annoy a lot of IP core vendors, but on the other side, why do the offer a so simple IP core for ~15,000 €? yes......
yesterday I saw a simple multiplier for only one use
XD
it was just an wrapper of the Xilinx macro
leduchuybk
@leduchuybk
Hi i'm new to this project. As i read down the Docs. this seems to be a library of IP core like Xilinx's or Altera . But I couldnt find any full list of IP core u can provide. Thanks
Patrick Lehmann
@Paebbels
@leduchuybk There is no full list of IP cores, because it's over 120 IPs. When you open the IP core documentation of PoC on ReadTheDocs.org, you'll see the full list of cores in the navigation tree:
image.png
If you search a specific core, you can use the search bar and e.g. search for pwm: https://poc-library.readthedocs.io/en/release/search.html?q=pwm&check_keywords=yes&area=default
image.png
If you can a specific question, you can also ask me here.
leduchuybk
@leduchuybk
thank for your reply. i'm a undergraduated student searching for projects to strengthen my code skills. so may i ask for your current ip u guys developing. i want to learn and contribute to the project. besides, i can see all the ip doc written in german. anywhere i can find the english version.
Patrick Lehmann
@Paebbels
Hi, to what German documentation are you referring? I was hoping that we never released any Germany documentation, otherwise we would need to translate it :).
Jevin Sweval
@jevinskie
Any updates on VLSI-EDA/PoC#62 ? I’d really like to get started using PoC
Jevin Sweval
@jevinskie
I’ve managed to get around a few issues and now the .files parser is erroring out on the alu prng .file expecting an include token on the first character of the file (a # comment)
Arman Galstyan
@AGalstyanK622
Hi all
who is interested in digital ic design?
Jevin Sweval
@jevinskie
Me! Haven’t heard a peep from @all in here for a while though
Patrick Lehmann
@Paebbels
@jevinskie I'm working on a new release. The library has been used in some projects at my company and we'll now release some changes and additions.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
Hi! I want to use the fifo in my project. I'm simulating it with VUnit and GHDL. I have this error:
/debug/fifo_ic_got.vhd:293:35: can't resolve overload for function call, slice or indexed name
/debug/fifo_ic_got.vhd:293:35: possible interpretations are:
../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned"
../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"
I'm trying to use only the the minimal files
GlenNicholls
@GlenNicholls
@qarlosalberto assuming you've configured PoC properly, this likely isn't an issue with GHDL or PoC. You probably aren't using the correct flags for GHDL

Try vu.set_compile_option('ghdl.a_flags', ['--ieee=synopsys', '-frelaxed-rules']). Some of the widely used, accepted styles, aren't technically compliant with the VHDL LRM. GHDL is much more strictly compliant to the LRM whereas many commercial simulators have default settings to de-escalate these LRM compliance issues as info/warnings simply because so many people use the non-standard IEEE libraries and those code styles. GHDL has the above flags to overcome these problems. I usually add the following line as well for simulation vu.set_sim_option('ghdl.elab_flags', ['--ieee=synopsys', '-frelaxed-rules'])

Also, make sure you're using the latest stable release and check their CI commands to see how they simulate with GHDL. Last time I checked, PoC uses GHDL for simulation so I know their code will work with that simulator

Carlos Alberto Ruiz Naranjo
@qarlosalberto
thank you @GlenNicholls !!!! :)