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  • Oct 23 22:37
    eine commented #686
  • Oct 21 10:27
    arnfol commented #687
  • Oct 21 10:18
    arnfol opened #687
  • Oct 16 18:24
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  • Oct 16 18:06
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  • Oct 15 18:47
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  • Oct 01 20:18
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  • Oct 01 16:33
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  • Oct 01 06:03
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  • Sep 30 22:07
    eine commented #682
  • Sep 30 22:07

    eine on master

    Make runner.create_output_path … Rename TestRunner._create_outpu… Break out TestRunner._prepare_t… (compare)

  • Sep 30 22:07
    eine closed #682
  • Sep 30 19:38
    LarsAsplund commented #682
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eine
@eine
That was about Docker (and maybe flexlm), tho. Which is trickier because it allows to easily bypass licensing by setting a custom MAC addr in the container.
There was another more recent discussion about using XSim for designs targeting Intel devices, or the other way round.
Yet, maybe it was in a different room.
nfrancque
@nfrancque
https://gitter.im/VUnit/vunit?at=5e98b564a9ca1862063f188d Lars mentioned he uses it, but I can't tell if that is professionally or for evaluation only
Btw, has there been any further progress on xsim support that you know of, or are we waiting on xilinx to have better 2008 support?
eine
@eine
Actually, Carlos found out that Xilinx does not support some VHDL 1993 features required by VUnit.
nfrancque
@nfrancque
Had not realized that. That is unfortunate.
eine
@eine
OTOH, they have sent some email to the VASG regarding synthesis support of float packages.
However, I believe they have different engines for simulation and synthesis.
I wouldn't bet much on it, overall.
nfrancque
@nfrancque
I think you are right. The last information I saw was their simulator actually supported less of 2008 than the synthesizer, which is very weird.
eine
@eine
From my experience, it's similar in ModelSim/QuestaSim and Precision too, but Siemens'/Mentor's products have a better language support.
Anyway, the only motivation I see for using XSim is using Xilinx's encrypted IP. What I see around me is that the most professional users working on critial applications run away from those as fast as they can.
nfrancque
@nfrancque
Usually agree, depends on scenario. Some of their selectio components are part of secureip. And I believe you need a mixed language simulator to do any design IP (not just unisim). Not sure on that point, though.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
I remember someone was working on a project with VUnit + cocotb. What is the repository? ^ ^
The differences between them are explained in the README of my fork.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
thank you :)
Kaleb Barrett
@ktbarrett
@qarlosalberto Development of VUnit/cocotb integration on my end is on pause. I'm prioritizing improving the contributor and internal documentation, and laying out more high-level tasks and a roadmap on cocotb before that. We need it to be easier to work on before reaching a larger user base. There is a lot of work to be done on that project.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
ahh okok. Thank you @ktbarrett
GlenNicholls
@GlenNicholls
I am trying to get all the files for VUnit so I can use go-to-definition in VSC. If I glob("**.vhd") in the checkout location, will this be valid or is there anything I need to keep in mind when adding all VHDL sources?
eine
@eine
@GlenNicholls, currently, glob might be not recursive. Need to check that. :point_up: October 6, 2020 5:04 PM
GlenNicholls
@GlenNicholls
@eine I'm not talking about adding files to vunit, but instead to glob in a python script to find all VHDL sources in the vunit python package. I'm trying to create vhdl_ls.toml for rust_hdl with all VUnit sources
My question is more if I glob for all VHDL files, are there files that are deprecated and should not be added or specific files not valid in VHDL1993 for example?
eine
@eine
You can use glob("**.vhd", recursive=True and you'll get everything. Some sources are for any VHDL revision. Others are "duplicated" depending on the version. You can tell that from the namig. https://github.com/VUnit/vunit/tree/master/vunit/vhdl/data_types/src
In https://github.com/VUnit/vunit/blob/master/vunit/builtins.py you can see how VUnit adds all the files internally.
The issue with using glob is that you don't get any info about which library is each source expected to be built into.
GlenNicholls
@GlenNicholls

You can use glob("**.vhd", recursive=True and you'll get everything. Some sources are for any VHDL revision. Others are "duplicated" depending on the version. You can tell that from the namig. https://github.com/VUnit/vunit/tree/master/vunit/vhdl/data_types/src

Sweet, this is exactly what I was looking for. Thank you!

The issue with using glob is that you don't get any info about which library is each source expected to be built into.

For vunit this is fine since it's all one library. With OSVVM/JSON-for-VHDL in the vhdl dir I know I'll have to be careful.

eine
@eine

For vunit this is fine since it's all one library. With OSVVM/JSON-for-VHDL in the vhdl dir I know I'll have to be careful.

Exactly, I was thinking about OSVVM/JSON-for-VHDL. Do take a careful look at builtins.py, even if you write your own script.

are there files that are deprecated

The array package is deprecated, but not removed yet.

GlenNicholls
@GlenNicholls
Yeah, I will, I might also try to leverage initializing VUnit and having it spit out all the files, but this is kind of annoying with a bunch of try-excepts as I could just try-except import vunit when I want to get the location using vunit.__file__ to figure out where it is if it is installed.
eine
@eine
I am very interested on using VUnit without VUnit. That is being able to build and use VHDL sources in environments where Python is not available. For now, I initialise it with a rather trivial run.py script, and then add the libraries from vunit_out to GHDL through -P. That's not ideal, tho, because you actually need Python for building the libraries first.
However, I can build them in an ARM container and then transfer the libs to development boards.
GlenNicholls
@GlenNicholls

I am very interested on using VUnit without VUnit. That is being able to build and use VHDL sources in environments where Python is not available.

Can you expand on this? Where would you run into a situation like this?

eine
@eine
In development boards where GHDL runs but Python is poorly supported, and for users which explicitly refuse to use Python (there are still a few of those).
Overall, the point is that VUnit's Python runner and VHDL helpers libs are not dependent. Using the Python runner while ignoring VHDL libs is a supported workflow, because of the non-intrusive philosophy. However, using VHDL helpers without Python is not explicitly supported/documented.
eine
@eine
Other projects might want to import those libs only. I'm thinking about edalize, fusesoc, etc. Furthermore, OSVVM is providing a TCL based plumbing.
Should fusesoc be decoupled from edalize, it would allow defining VUnit's VHDL as a core with multiple filesets/libs, or as multiple cores. However, I don't think fusesoc is explicitly conceived for handling "simulation cores". That's what the discussion in eine/vhdl-cfg#1 is about.
I would expect rust_hdl, ghdl-lang-server, etc. to consume fusesoc files. Tristan did already ask Olof about it.
Olof Kindgren, not Kraigher.
GlenNicholls
@GlenNicholls

Overall, the point is that VUnit's Python runner and VHDL helpers libs are not dependent. Using the Python runner while ignoring VHDL libs is a supported workflow, because of the non-intrusive philosophy. However, using VHDL helpers without Python is not explicitly supported/documented.

Gotcha, that makes sense. Yeah, I guess what I'm trying to do would benefit from this. I guess another benefit would be for vendors to test VUnit VHDL sources without needing python.

Other projects might want to import those libs only. I'm thinking about edalize, fusesoc, etc. Furthermore, OSVVM is providing a TCL based plumbing.

To preach to the quire, I think standardizing a JSON/similar format for HDL/IP files that can be used for building and simulating with multiple tools would be hugely beneficial. We've had this conversation multiple times, but this is just another thing that format would benefit.

eine
@eine

We've had this conversation multiple times, but this is just another thing that format would benefit.

I've been lately looking into fusesoc more seriously. You know, always more things to do than spare time... But the point is that having any tool other than edalize use fusesoc would be the first step for making fusesoc's format that unified/standard JSON we need. That other tool can be GHDL, VUnit, tsfpga, PyFPGA, any...

Yet, it is hard to ask those developers to do the effort without knowing whether modifications to fusesoc would be constrained by the only oficial backend.
OTOH, as we discussed in VHDL/General some months ago, fusesoc is purely declarative. HDL projects do benefit from imperative configuration workflows.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
is there a way to create an integer_array_t 2D array and to append 1D array? or similar
GlenNicholls
@GlenNicholls
@qarlosalberto do you mean type integer_array_t is array (natural range<>, natural range<>) of integer;? You cannot directly append a 1D array to that because it would be type integer_vector_t is array(natural range<>) of integer, but you could write a function/procedure to append.

If you use your vector type in the 2D declaration like this

type integer_vector is array(natural range<>) of integer;
type integer_vector_2d is array(natural range<>) of integer_vector;

Then it would work, you could also do it with subtype. The above I'm pretty sure is only valid in 2008+.

eine
@eine

Since VHDL does not allow dynamically changing the size of the objects, no matter how you do it, a new object needs to be created. Now, the question is: does VHDL provide enough language features for the following?

  • Get the ranges of a multidimensional array.
  • Create a new multidimensional array by adding the ranges of multiple existing multidimensional arrays.
  • Traverse the rows/columns of a multidimensional array and assing them to another multidimensional array.

My understanding is that something similar to the following should be possible:

type integer_array_2D_t is array (natural range <>, natural range <>) of integer;
type integer_array_1D_t is array (natural range <>) of integer;

signal 2Darr : integer_array_2D_t(0 to 5, 0 to 10);
signal 1Darr : integer_array_1D_t(0 to 10);

signal merge : integer_array_2D_t(2Darr'range(0)'left to 2Darr'range(1)'right + 1, 2Darr'range(1));

begin

merge(2Darr'range(0), 2Darr'range(1)) <= 2Darr;
merge(2Darr'range(0)+1, 1Darr'range) <= 1Darr;

If you wanted 2Darr to hold the new (larger) matrix, 2Darr would need to be an access type. Unfortunately, it is currently not possible to get an access from merge (IEEE-P1076/VHDL-Issues#14). Hence, that would also need to be an access type. All this makes it hard to track/understand for synthesis.

Nevertheless. Using accesses for having "dynamic arrays/vectors" is wat VUnit does internally. You have many examples about it in the codebase.

With regard to multidimensional arrays, slices, etc. see:

Carlos Alberto Ruiz Naranjo
@qarlosalberto
Thank you very much!!! :) :) @eine @GlenNicholls