VUnit/vunit

VUnit is a unit testing framework for VHDL & SystemVerilog

GlenNicholls

@GlenNicholls

some years ago GHDL was distributed as a Debian package, but because it included non-free IEEE libs it was removed. Then, Tristan wrote openieee to allow a roughly functional package of GHDL + libs to be distributed through Debian repos. Now that IEEE libs are open source, openieee should not be required.

Ahhh okay, I see. Probably explains why I had so many difficulties with GHDL a few years ago when I first tried to use it. Thanks for the history!

Rafael Pereira

@rafaelnp

@eine My first message contained the error on Arch Linux, the one below is from Ubuntu, similar, but not the same:

=== Command output: ===
/usr/bin/ghdl-mcode:warning: library ieee does not exists for v08
/usr/local/lib/python3.7/dist-packages/vunit/vhdl/string_ops/src/string_ops.vhd:9:9: cannot find resource library "ieee"
/usr/local/lib/python3.7/dist-packages/vunit/vhdl/string_ops/src/string_ops.vhd:10:10: unit "std_logic_1164" not found in library "ieee"
Compile failed

eine

@eine

@rafaelnp are you trying to execute one of VUnit's examples? Or your own?

Bradley Harden

@bradleyharden

A colleague of mine is trying to use --export-json to get started with rust_hdl. I have done neither before, so I'm having trouble helping him. VUnit is choking on the vendor libraries. Their location is called out in the modelsim.ini file, and there are no complaints when simulating the design. But when he tried to --export-json, VUnit says it can't find the libraries.

Any thoughts? Is this a possible bug? Or is he not doing something right?

Wait, maybe that makes sense. There are no source files for the pre-compiled vendor libs, so it doesn't make sense for them to be included, right?

Rafael Pereira

@rafaelnp

@eine the examples from the user_guide.

@eine @GlenNicholls I was able to find the root cause, as pointed by @eine. I downloaded the ghdl source code, compiled and installed and added it to the $PATH, and now it works. I compared both package contents (Arch and Ubuntu) to the manually installed files, and there are binary (*.o) and VHDL files missing. Thanks for your help. :)

GlenNicholls

@GlenNicholls

@all does anyone have any public resources for combining multiple verification components in a single BFM? I have a large design I'm currently verifying and the testbench is getting pretty ugly with all of VC's and message passing. I've got AXI master/slaves, AXI stream, UART, AXI GPIO, and memory and I would like to package this in a single BFM to make it easier to maintain. Unfortunately, the component I'm working with will be used in an even larger design so I'm trying to find a reasonable way to put this in a single BFM such that it can be directly instantiated later without copying/pasting so much code. I checked tsfpga and it doesn't look like they have anything like this and searching GitHub isn't yielding anything.

NanooooK

@NanooooK

Is there a way from a VHDL testbench to retrieve the information provided by Python add_config? I'm looking to retrieve the name so I can pass it to the file_handler parameters. I've checked the documentation but the only information that I've found that could be extracted from the runner are output_path and tb_path

Lars Asplund

@LarsAsplund

@all Nice voting for https://forums.xilinx.com/t5/Simulation-and-Verification/Add-support-for-VUnit/td-p/1098552. We're

Lars Asplund

@LarsAsplund

@NanooooK No, you would have to input the configuration name as an extra generic.

NanooooK

@NanooooK

Ok, I'll do that then. Thanks

Yatekii

@Yatekii

@LarsAsplund well unfortunatley I think you can forget this ...

they had 12 years time to implement 2008 and it still is not

eine

@eine

@Yatekii, funnily enough, the features that are being requested are VHDL 1993 features, NOT VHDL 2008. They had 27 years to do it..

Still, praying is free (as in free beer).

T. Meissner

@tmeissner

Hope dies last 🙂

But I’m very glad to have Questa at work.

eine

@eine

In fact, I think I have never used Vivado's simulator. I used ISE's. But I'm also glad to have both GHDL and Questa (with some setup annoyances).

Yatekii

@Yatekii

@eine it is 100% paid as in you pay a premium for the cores.

do you think they work on the tools for free? :D

eine

@eine

@Yatekii, I'm not sure I understand what you mean.

Yatekii

@Yatekii

so they have to pay their engineers for developing vivado etc.

how do you think they are paid?

with revenue from sold chips

and who pays for the chips? yes, you, the vivado user

it is 100% not free

eine

@eine

Oh. Sure! The point is that they do NOT pay their engineers for developing VHDL support, because they believe the revenue is not worth.

Yatekii

@Yatekii

yeah the problem is that afaik they are the market leader by large margin

eine

@eine

The point is whether that's true or just a very subjective and interested analysis of the market.

Yatekii

@Yatekii

at least in perf/architecture, dunno in revenue

so they don't have to improve

which is stupid

and I don't have the money for modelsim tbh

but tbh, no chip manufacturer procides even halfways decent devtools lol

there is no chip manufactuer that provides a proper ide that is not eclipse based or absolute garbage in any other way lol

T. Meissner

@tmeissner

Most of the FPGA vendor tools are crap ;)

eine

@eine

I think that the question of it being free or paid is tangential to the quality of the software. Both GHDL and Questasim are better simulators than XSIM. One is free and the other one is not.

Yatekii

@Yatekii

well altera at least provides a free modelsim version

and afaik 2008 support is way better with other vendors. we at least used it with altera chips

T. Meissner

@tmeissner

The best case is when they provide third party tools for simulation or synthesis, as Lattice & Microsemi do

Yatekii

@Yatekii

@eine well I would use GHDL and even contribute, but it's impossible to use with vivado, because ofc all their macros are SV

eine

@eine

I agree with both comments about eclipse-based crap and about providing licenses for third-party tools (as Lattice).

T. Meissner

@tmeissner

Microsemi provide Modelsim ME, now even with PLUS (dual language)

Yatekii

@Yatekii

well I see a glimmer of hope on the horizon now with vscode etc. and rust emerging :) we'll see. and I hope the same happens for HDL & FPGAs :)

eine

@eine

@eine well I would use GHDL and even contribute, but it's impossible to use with vivado, because ofc all their macros are SV

You can use GHDL as a preprocessor to write VHDL 2008 designs and have them implemented by Vivado. This is not the issue that motivated this conversation (since running VUnit requires unsupported VHDL 1993 features). But it is a work around some other poor features of Vivado.

T. Meissner

@tmeissner

But I never used, so I think, it's performance limited as all "free" Modelsim versions

eine

@eine

well I see a glimmer of hope on the horizon now with vscode etc. and rust emerging :) we'll see. and I hope the same happens for HDL & FPGAs :)

I believe that VUnit + GHDL + VSCode is a very interesting ecosystem. Integration is not there yet... but TerosHDL and https://marketplace.visualstudio.com/items?itemName=hbohlin.vunit-test-explorer are going in the good direction.

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