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  • 14:49
    Marek-ADT commented #862
  • 12:32
    LarsAsplund synchronize #883
  • 12:32

    LarsAsplund on vunit_event

    Replaced AXI stream synchroniza… Add support for deferring check… Add support for ordering of pre… and 6 more (compare)

  • Jan 29 21:29
    LarsAsplund synchronize #883
  • Jan 29 21:29

    LarsAsplund on vunit_event

    Update event. Replaced AXI stream synchroniza… Add support for deferring check… and 7 more (compare)

  • Jan 28 20:07
    LarsAsplund synchronize #883
  • Jan 28 20:07

    LarsAsplund on vunit_event

    Added string decoration functio… Make check result function an a… Added event mechanism. and 12 more (compare)

  • Jan 27 23:15
    LarsAsplund commented #862
  • Jan 27 13:54
    Marek-ADT commented #862
  • Jan 27 13:43
    Andy-Darlington commented #862
  • Jan 27 13:06
    LarsAsplund commented #862
  • Jan 27 10:24
    Marek-ADT commented #862
  • Jan 27 10:19
    Marek-ADT commented #862
  • Jan 27 10:18
    Marek-ADT commented #862
  • Jan 26 19:10
    vogma edited #894
  • Jan 26 19:08
    vogma edited #894
  • Jan 26 17:29
    vogma opened #894
  • Jan 25 21:18
    LarsAsplund commented #862
  • Jan 24 21:13

    eine on master

    readme: update shield syntax (b… (compare)

  • Jan 24 15:55
    LarsAsplund closed #893
Rafael Pereira
@rafaelnp
@eine @GlenNicholls I was able to find the root cause, as pointed by @eine. I downloaded the ghdl source code, compiled and installed and added it to the $PATH, and now it works. I compared both package contents (Arch and Ubuntu) to the manually installed files, and there are binary (*.o) and VHDL files missing. Thanks for your help. :)
GlenNicholls
@GlenNicholls
@all does anyone have any public resources for combining multiple verification components in a single BFM? I have a large design I'm currently verifying and the testbench is getting pretty ugly with all of VC's and message passing. I've got AXI master/slaves, AXI stream, UART, AXI GPIO, and memory and I would like to package this in a single BFM to make it easier to maintain. Unfortunately, the component I'm working with will be used in an even larger design so I'm trying to find a reasonable way to put this in a single BFM such that it can be directly instantiated later without copying/pasting so much code. I checked tsfpga and it doesn't look like they have anything like this and searching GitHub isn't yielding anything.
NanooooK
@NanooooK
Is there a way from a VHDL testbench to retrieve the information provided by Python add_config? I'm looking to retrieve the name so I can pass it to the file_handler parameters. I've checked the documentation but the only information that I've found that could be extracted from the runner are output_path and tb_path
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Lars Asplund
@LarsAsplund
@NanooooK No, you would have to input the configuration name as an extra generic.
NanooooK
@NanooooK
Ok, I'll do that then. Thanks
Yatekii
@Yatekii
@LarsAsplund well unfortunatley I think you can forget this ...
they had 12 years time to implement 2008 and it still is not
eine
@eine
@Yatekii, funnily enough, the features that are being requested are VHDL 1993 features, NOT VHDL 2008. They had 27 years to do it..
Still, praying is free (as in free beer).
T. Meissner
@tmeissner
Hope dies last 🙂
But I’m very glad to have Questa at work.
eine
@eine
In fact, I think I have never used Vivado's simulator. I used ISE's. But I'm also glad to have both GHDL and Questa (with some setup annoyances).
Yatekii
@Yatekii
@eine it is 100% paid as in you pay a premium for the cores.
do you think they work on the tools for free? :D
eine
@eine
@Yatekii, I'm not sure I understand what you mean.
Yatekii
@Yatekii
so they have to pay their engineers for developing vivado etc.
how do you think they are paid?
with revenue from sold chips
and who pays for the chips? yes, you, the vivado user
it is 100% not free
eine
@eine
Oh. Sure! The point is that they do NOT pay their engineers for developing VHDL support, because they believe the revenue is not worth.
Yatekii
@Yatekii
yeah the problem is that afaik they are the market leader by large margin
eine
@eine
The point is whether that's true or just a very subjective and interested analysis of the market.
Yatekii
@Yatekii
at least in perf/architecture, dunno in revenue
so they don't have to improve
which is stupid
and I don't have the money for modelsim tbh
but tbh, no chip manufacturer procides even halfways decent devtools lol
there is no chip manufactuer that provides a proper ide that is not eclipse based or absolute garbage in any other way lol
T. Meissner
@tmeissner
Most of the FPGA vendor tools are crap ;)
eine
@eine
I think that the question of it being free or paid is tangential to the quality of the software. Both GHDL and Questasim are better simulators than XSIM. One is free and the other one is not.
Yatekii
@Yatekii
well altera at least provides a free modelsim version
and afaik 2008 support is way better with other vendors. we at least used it with altera chips
T. Meissner
@tmeissner
The best case is when they provide third party tools for simulation or synthesis, as Lattice & Microsemi do
Yatekii
@Yatekii
@eine well I would use GHDL and even contribute, but it's impossible to use with vivado, because ofc all their macros are SV
eine
@eine
I agree with both comments about eclipse-based crap and about providing licenses for third-party tools (as Lattice).
T. Meissner
@tmeissner
Microsemi provide Modelsim ME, now even with PLUS (dual language)
Yatekii
@Yatekii
well I see a glimmer of hope on the horizon now with vscode etc. and rust emerging :) we'll see. and I hope the same happens for HDL & FPGAs :)
eine
@eine

@eine well I would use GHDL and even contribute, but it's impossible to use with vivado, because ofc all their macros are SV

You can use GHDL as a preprocessor to write VHDL 2008 designs and have them implemented by Vivado. This is not the issue that motivated this conversation (since running VUnit requires unsupported VHDL 1993 features). But it is a work around some other poor features of Vivado.

T. Meissner
@tmeissner
But I never used, so I think, it's performance limited as all "free" Modelsim versions
eine
@eine

well I see a glimmer of hope on the horizon now with vscode etc. and rust emerging :) we'll see. and I hope the same happens for HDL & FPGAs :)

I believe that VUnit + GHDL + VSCode is a very interesting ecosystem. Integration is not there yet... but TerosHDL and https://marketplace.visualstudio.com/items?itemName=hbohlin.vunit-test-explorer are going in the good direction.

Yatekii
@Yatekii
yeah, except that sadly, for this to work, i cannot use xilinx macros atm :) as soon as you need a bram or the likes you fuked :D
@eine well does GHDL understand to use macros and properly forward them?
@eine hmm I think vunit requires some 2008 stuff that's unsupported too, like extensive generics, no?
eine
@eine

yeah, except that sadly, for this to work, i cannot use xilinx macros atm :) as soon as you need a bram or the likes you fuked :D

Can't you have BRAMs inferred instead of instantiated explicitly?

well does GHDL understand to use macros and properly forward them?

AFAIK, GHDL allows to simulate any Vivado design, as long as you don't need encrypted IP.

GHDL does not support mixed-language. But most vendor libs are supported, as long as models are available in VHDL. E.g., Lattice provides Verilog models only for some devices.

hmm I think vunit requires some 2008 stuff that's unsupported too, like extensive generics, no?

It does not. Of course, it is strongly suggested to have a simulator with decent VHDL 2008 support. However, the very basic features of VUnit (being a test runner and manager) works with VHDL 1993.

If you want to use some more advanced resources, such as the Verification Components Library, VHDL 2008 is required.