LarsAsplund on master
Fix issue #794. This solves th… (compare)
py run.py '<library_name_set>.<testbench_name_set>.<test-case-name_set>' -v
You can pass the dictionary as string or as the path to a file. Optionally, you can encode the string:
TB.get_tests("stringified*").set_generic("tb_cfg", JSON_STR) TB.get_tests("b16encoded stringified*").set_generic("tb_cfg", b16encode(JSON_STR)) TB.get_tests("JSON file*").set_generic("tb_cfg", JSON_FILE) TB.get_tests("b16encoded JSON file*").set_generic("tb_cfg", b16encode(str(TEST_PATH / JSON_FILE)))
You only need one of those. The four of them are used in the example for illustration.
Q> While running simulation using ModelSim, I am always getting the warning: " Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." and I want to get rid of this warning. How can I do it?
What I did and is not working>
Is there any other things I can try out from run.py?
@dpaul24 You're using
allow_empty=True. Is that because it didn't find any testbenches? Note that the sim option only applies to testbenches added before the sim option was set.
Well I did not give it much thought, I just think it would be safe to use the TRUE setting. btw - All my TBs are loaded I use vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True)
constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(
data_length => data_width
user_length => 1
user_lengthand all other parameters.
I have another question. This time about the pop function from AXI stream.
I want to push and pop the tuser flag on axi stream. Push works fine, but I can't pop it.
It gives me the following error, but I don' t know why.
(vcom-1600) No feasible entries for subprogram "pop_axi_stream".
I configured the master and slave the same way:
constant master_axi_stream_bus : axi_stream_master_t := new_axi_stream_master( data_length => data_width, user_length => tuser_width ); constant slave_axi_stream_bus : axi_stream_slave_t := new_axi_stream_slave( data_length => data_width, user_length => tuser_width );
variable user : std_logic_vector(tuser_width-1 downto 0);
And my pop function looks like this:
pop_axi_stream(net, slave_axi_stream_bus, tdata => received_data, tlast => last, tuser => user);
Without the tuser all works fine.
Does anyone perhaps have a suggestion?
so I have what is possibly a very silly query but I am unsure how to go about solving it all the same.
I have a vhdl pkg with constants that govern the slv bit widths in my design. I cannot pass these bitwidths down via generics as these widths are specifications for bitwidths in an slv array.
The majority of my tests run with one bit width, but I have a few cases where I require a different one.
I want to know whether I can have a set up as follows:
Is this possible? I've not seen any way to remove tb configurations.