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  • Jan 17 20:21
    eine labeled #796
  • Jan 17 20:19
    o-uggla opened #796
  • Jan 17 08:26
    olafvandenberg commented #573
  • Jan 14 23:03
    LarsAsplund commented #793
  • Jan 14 12:14
    nfrancque commented #793
  • Jan 14 12:14
    nfrancque commented #793
  • Jan 14 09:16
    hcommin commented #573
  • Jan 14 08:22
    eschmidscs commented #573
  • Jan 14 08:14
    eschmidscs synchronize #792
  • Jan 14 08:09
    eschmidscs synchronize #792
  • Jan 14 07:44
    LarsAsplund labeled #795
  • Jan 14 07:44
    LarsAsplund opened #795
  • Jan 14 07:40
    LarsAsplund closed #794
  • Jan 14 07:40
    LarsAsplund commented #794
  • Jan 14 07:38
    tasgomes commented #793
  • Jan 14 07:06

    LarsAsplund on master

    Fix issue #794. This solves th… (compare)

  • Jan 14 05:58

    LarsAsplund on issue-794

    Fix issue #794. This solves th… (compare)

  • Jan 13 22:10

    LarsAsplund on issue-794

    Fix issue #794. This solves th… (compare)

  • Jan 13 21:50

    LarsAsplund on issue-794

    Fix issue #794. This solves th… (compare)

  • Jan 13 21:33
    cmarqu commented #793
Unai Martinez-Corral
@umarcor
py run.py '<library_name_set>.<testbench_name_set>.<test-case-name_set>' -v
That's annoying but standard terminal/shell behaviour.
dpaul
@dpaul24
@umarcor Ah ha! I got it now, thank you.
Either use no blank spaces or use quotes "....".
Lars Asplund
@LarsAsplund
@dpaul24 In the early days of VUnit, prior to the first public release, we had internal discussions about test case naming. Whether we should have arbitrary strings or restrict ourselves to identifier naming rules. SW unit test frameworks typically have identifier rules so there is a familarity with that. However, in the typical unit testing framework the test case is represented by a method or a function in which case naming is limited. To allow naming strategies that are very verbose, for example those promoted by BDD, we decided to go for an approach that allows for natural language naming. Some people still prefer identifier naming but VUnit doesn't impose such restrictions.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
is it possible to pass a dictionary as generic from run.py to ModelSim test?
Unai Martinez-Corral
@umarcor
@qarlosalberto check the json4vhdl example

You can pass the dictionary as string or as the path to a file. Optionally, you can encode the string:

TB.get_tests("stringified*")[0].set_generic("tb_cfg", JSON_STR)
TB.get_tests("b16encoded stringified*")[0].set_generic("tb_cfg", b16encode(JSON_STR))
TB.get_tests("JSON file*")[0].set_generic("tb_cfg", JSON_FILE)
TB.get_tests("b16encoded JSON file*")[0].set_generic("tb_cfg", b16encode(str(TEST_PATH / JSON_FILE)))

You only need one of those. The four of them are used in the example for illustration.

Carlos Alberto Ruiz Naranjo
@qarlosalberto
thanks!! :)
Unai Martinez-Corral
@umarcor
Encoding the strings allows working around the limitations that some simulators have when parsing non-trivial strings.
Hence, regardless of using JSON and JSON-for-VHDL, it is some to keep in mind.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
it's a very useful example :D
dpaul
@dpaul24

Q> While running simulation using ModelSim, I am always getting the warning: " Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." and I want to get rid of this warning. How can I do it?

What I did and is not working>

  1. In my run.py, I have added the following which fails to take effect...
    vu_prj.set_sim_option("modelsim.init_files.after_load", ["turn_off_some_warnings.do"])
    vu_prj.set_sim_option("modelsim.init_files.before_run", ["turn_off_some_warnings.do"])
  2. I have also tried using vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True) and this also fails to work.

Is there any other things I can try out from run.py?

Note that if I run the DO file turn_off_some_warnings.do at the ModelSim prompt before the run -all command then I get what I want to have.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
ui.set_sim_option("modelsim.init_files.after_load", ["modelsim.do"])
works for me
Lars Asplund
@LarsAsplund
@dpaul24 You're using allow_empty=True. Is that because it didn't find any testbenches? Note that the sim option only applies to testbenches added before the sim option was set.
dpaul
@dpaul24

ui.set_sim_option("modelsim.init_files.after_load", ["modelsim.do"])

Well I am loading a waveform file, vu_prj.set_sim_option('modelsim.init_files.after_load', ["vunit_wave.do"]) and it works, so I am more confused why another DO is not taking effect correctly.

@dpaul24 You're using allow_empty=True. Is that because it didn't find any testbenches? Note that the sim option only applies to testbenches added before the sim option was set.

Well I did not give it much thought, I just think it would be safe to use the TRUE setting. btw - All my TBs are loaded I use vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True)

Dominic
@abaebae
Does VUnit or OSVVM have an equivalent of the SystemVerilog sort for arrays?
dpaul
@dpaul24
Ok the vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True) works, after I did a --clean run.
Carlos Alberto Ruiz Naranjo
@qarlosalberto
does VUnit use the same environment variable for Questa and Modelsim (VUNIT_MODELSIM_PATH) ?
Lars Asplund
@LarsAsplund
Yes
Carlos Alberto Ruiz Naranjo
@qarlosalberto
ok, thanks
Jim Lewis
@JimLewis
@abaebae For integer vectors, OSVVM's SortListPkg_int has a sort for integer vector. It is setup for VHDL-2019 where we will be able to sort any type of array.
Jim Lewis
@JimLewis
and a reverse sort
dasHorst99
@dasHorst99
Hi,
I want to use vunit and now I am a bit stuck. I want to use the AXI master VC and there tuser. Which size should it have or can i assign it any size i need?
Lars Asplund
@LarsAsplund
dasHorst99
@dasHorst99
Thank you!
I am not a pro in VHDL so please forgive my question:
Do I have to change it in that file or can I change it also throughout other methods?

Like so?

constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(
data_length => data_width
user_length => 1
);

Lars Asplund
@LarsAsplund
You would do it as you suggest. It is a fix "physical" setting for that bus so you cannot change it dynamically. If you have several instances of AXI stream masters then you have several of these constants that have their own settings for user_length and all other parameters.
dasHorst99
@dasHorst99
Ok, thank very much!
Carlos Alberto Ruiz Naranjo
@qarlosalberto
is it possible to simulate with ModelSim + VUnit a module with an encrypted .edn file?
@GlenNicholls you got it?
Lars Asplund
@LarsAsplund
It is possible. The problem is that since VUnit can't read the encrypted file it doesn't know its dependencies and can't figure out compile order. The typical use case though is a third-party IP which doesn't change often. As such it doesn't really need to be involved in dependency checking. Use whatever compile method the vendor provides and then you add that library as an external library using https://vunit.github.io/py/vunit.html#vunit.ui.VUnit.add_external_library
Carlos Alberto Ruiz Naranjo
@qarlosalberto
Ok, thanks!!!
dasHorst99
@dasHorst99
I have a question on how to use AXI Lite Master. As far as I undertsand I can configure AXI Stream VC via push with the axi_stream_master_t. How do I have to do it with AXI Lite?
Is it that I have to use for example this (from the axi dma example):
constant axil_bus : bus_master_t := new_bus(data_length => 32, address_length => 32);
and write it to the AXI Lite MAster with this:
write_bus(net, axil_bus, src_address_reg_addr, src_addr);
?
dasHorst99
@dasHorst99

I have another question. This time about the pop function from AXI stream.
I want to push and pop the tuser flag on axi stream. Push works fine, but I can't pop it.
It gives me the following error, but I don' t know why.
(vcom-1600) No feasible entries for subprogram "pop_axi_stream".
I configured the master and slave the same way:

constant master_axi_stream_bus : axi_stream_master_t := new_axi_stream_master(
    data_length => data_width,
    user_length => tuser_width
  );
  constant slave_axi_stream_bus  : axi_stream_slave_t  := new_axi_stream_slave(
    data_length => data_width,
    user_length => tuser_width
  );

The tuser:

variable user           : std_logic_vector(tuser_width-1 downto 0);

And my pop function looks like this:

pop_axi_stream(net, slave_axi_stream_bus, tdata => received_data, tlast => last, tuser => user);

Without the tuser all works fine.
Does anyone perhaps have a suggestion?

Talon
@talonmyburgh

Hi all,
so I have what is possibly a very silly query but I am unsure how to go about solving it all the same.

I have a vhdl pkg with constants that govern the slv bit widths in my design. I cannot pass these bitwidths down via generics as these widths are specifications for bitwidths in an slv array.
The majority of my tests run with one bit width, but I have a few cases where I require a different one.
I want to know whether I can have a set up as follows:

  • start with the one bit width and its tb_configs.
  • run vu.main()
  • mangle the package to get the new bitwidth
  • re-compile the package.
  • add the tb_configs for this new bitwidth
  • remove the previous tb_configs
  • run vu.main() again.

Is this possible? I've not seen any way to remove tb configurations.

Lars Asplund
@LarsAsplund
@dasHorst99 To your first question: It looks like you're on the right path. In general I would also recommend looking at the tests that we use to verify the VCs. They are also open source and very much serves as executable documentation for the use of the tested VC. For example: https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/test/tb_axi_lite_master.vhd
Lars Asplund
@LarsAsplund
@talonmyburgh I'm not sure I fully understand the context. Is it VHDL that prevents you from using generics or is it a policy that you should keep all parameterisation in a global package?
Talon
@talonmyburgh
@LarsAsplund I'm required to use older versions of VHDL (<2008) in order to use Vivado correctly. Early version do not allow for elements of an array to be unconstrained. So in my design we have an interface type with slv's in it that have bitwidths specified by a package. I cannot make use of this interface and pass down the bitwidths via generics.
dasHorst99
@dasHorst99
@LarsAsplund
Thank very much!
Unai Martinez-Corral
@umarcor
@talonmyburgh you can do VHDL 2008 -> ghdl synth -> VHDL 1993 -> Vivado, in order to use modern VHDL features without being limited by the poor support in Vivado.