VUnit/vunit

VUnit is a unit testing framework for VHDL & SystemVerilog

Unai Martinez-Corral

@umarcor

Hence, regardless of using JSON and JSON-for-VHDL, it is some to keep in mind.

Carlos Alberto Ruiz Naranjo

@qarlosalberto

it's a very useful example :D

dpaul

@dpaul24

Q> While running simulation using ModelSim, I am always getting the warning: " Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)." and I want to get rid of this warning. How can I do it?

What I did and is not working>

In my run.py, I have added the following which fails to take effect...
vu_prj.set_sim_option("modelsim.init_files.after_load", ["turn_off_some_warnings.do"])
vu_prj.set_sim_option("modelsim.init_files.before_run", ["turn_off_some_warnings.do"])
I have also tried using vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True) and this also fails to work.

Is there any other things I can try out from run.py?

Note that if I run the DO file turn_off_some_warnings.do at the ModelSim prompt before the run -all command then I get what I want to have.

Carlos Alberto Ruiz Naranjo

@qarlosalberto

ui.set_sim_option("modelsim.init_files.after_load", ["modelsim.do"])

works for me

Lars Asplund

@LarsAsplund

@dpaul24 You're using allow_empty=True. Is that because it didn't find any testbenches? Note that the sim option only applies to testbenches added before the sim option was set.

dpaul

@dpaul24

ui.set_sim_option("modelsim.init_files.after_load", ["modelsim.do"])

Well I am loading a waveform file, vu_prj.set_sim_option('modelsim.init_files.after_load', ["vunit_wave.do"]) and it works, so I am more confused why another DO is not taking effect correctly.

@dpaul24 You're using allow_empty=True. Is that because it didn't find any testbenches? Note that the sim option only applies to testbenches added before the sim option was set.

Well I did not give it much thought, I just think it would be safe to use the TRUE setting. btw - All my TBs are loaded I use vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True)

Dominic

@abaebae

Does VUnit or OSVVM have an equivalent of the SystemVerilog sort for arrays?

dpaul

@dpaul24

Ok the vu_prj.set_sim_option("disable_ieee_warnings", True, allow_empty=True) works, after I did a --clean run.

Carlos Alberto Ruiz Naranjo

@qarlosalberto

does VUnit use the same environment variable for Questa and Modelsim (VUNIT_MODELSIM_PATH) ?

Lars Asplund

@LarsAsplund

Yes

Carlos Alberto Ruiz Naranjo

@qarlosalberto

ok, thanks

Jim Lewis

@JimLewis

@abaebae For integer vectors, OSVVM's SortListPkg_int has a sort for integer vector. It is setup for VHDL-2019 where we will be able to sort any type of array.

Jim Lewis

@JimLewis

and a reverse sort

dasHorst99

@dasHorst99

Hi,
I want to use vunit and now I am a bit stuck. I want to use the AXI master VC and there tuser. Which size should it have or can i assign it any size i need?

Lars Asplund

@LarsAsplund

@dasHorst99 You can set the length when creating the master, see https://github.com/VUnit/vunit/blob/96a24b38ba1553f520beb81f26753ca85dafb707/vunit/vhdl/verification_components/src/axi_stream_pkg.vhd#L163

dasHorst99

@dasHorst99

Thank you!

I am not a pro in VHDL so please forgive my question:
Do I have to change it in that file or can I change it also throughout other methods?

Like so?

constant master_axi_stream : axi_stream_master_t := new_axi_stream_master(
data_length => data_width
user_length => 1
);

Lars Asplund

@LarsAsplund

You would do it as you suggest. It is a fix "physical" setting for that bus so you cannot change it dynamically. If you have several instances of AXI stream masters then you have several of these constants that have their own settings for user_length and all other parameters.

dasHorst99

@dasHorst99

Ok, thank very much!

Carlos Alberto Ruiz Naranjo

@qarlosalberto

is it possible to simulate with ModelSim + VUnit a module with an encrypted .edn file?

@GlenNicholls you got it?

Lars Asplund

@LarsAsplund

It is possible. The problem is that since VUnit can't read the encrypted file it doesn't know its dependencies and can't figure out compile order. The typical use case though is a third-party IP which doesn't change often. As such it doesn't really need to be involved in dependency checking. Use whatever compile method the vendor provides and then you add that library as an external library using https://vunit.github.io/py/vunit.html#vunit.ui.VUnit.add_external_library

Carlos Alberto Ruiz Naranjo

@qarlosalberto

Ok, thanks!!!

dasHorst99

@dasHorst99

I have a question on how to use AXI Lite Master. As far as I undertsand I can configure AXI Stream VC via push with the axi_stream_master_t. How do I have to do it with AXI Lite?

Is it that I have to use for example this (from the axi dma example):
constant axil_bus : bus_master_t := new_bus(data_length => 32, address_length => 32);

and write it to the AXI Lite MAster with this:
write_bus(net, axil_bus, src_address_reg_addr, src_addr);
?

dasHorst99

@dasHorst99

I have another question. This time about the pop function from AXI stream.
I want to push and pop the tuser flag on axi stream. Push works fine, but I can't pop it.
It gives me the following error, but I don' t know why.
(vcom-1600) No feasible entries for subprogram "pop_axi_stream".
I configured the master and slave the same way:

constant master_axi_stream_bus : axi_stream_master_t := new_axi_stream_master(
    data_length => data_width,
    user_length => tuser_width
  );
  constant slave_axi_stream_bus  : axi_stream_slave_t  := new_axi_stream_slave(
    data_length => data_width,
    user_length => tuser_width
  );

The tuser:

variable user           : std_logic_vector(tuser_width-1 downto 0);

And my pop function looks like this:

pop_axi_stream(net, slave_axi_stream_bus, tdata => received_data, tlast => last, tuser => user);

Without the tuser all works fine.
Does anyone perhaps have a suggestion?

Talon

@talonmyburgh

Hi all,
so I have what is possibly a very silly query but I am unsure how to go about solving it all the same.

I have a vhdl pkg with constants that govern the slv bit widths in my design. I cannot pass these bitwidths down via generics as these widths are specifications for bitwidths in an slv array.
The majority of my tests run with one bit width, but I have a few cases where I require a different one.
I want to know whether I can have a set up as follows:

start with the one bit width and its tb_configs.
run vu.main()
mangle the package to get the new bitwidth
re-compile the package.
add the tb_configs for this new bitwidth
remove the previous tb_configs
run vu.main() again.

Is this possible? I've not seen any way to remove tb configurations.

Lars Asplund

@LarsAsplund

@dasHorst99 To your first question: It looks like you're on the right path. In general I would also recommend looking at the tests that we use to verify the VCs. They are also open source and very much serves as executable documentation for the use of the tested VC. For example: https://github.com/VUnit/vunit/blob/master/vunit/vhdl/verification_components/test/tb_axi_lite_master.vhd

For your second question you can have a look at this test case: https://github.com/VUnit/vunit/blob/96a24b38ba1553f520beb81f26753ca85dafb707/vunit/vhdl/verification_components/test/tb_axi_stream.vhd#L204

Lars Asplund

@LarsAsplund

@talonmyburgh I'm not sure I fully understand the context. Is it VHDL that prevents you from using generics or is it a policy that you should keep all parameterisation in a global package?

Talon

@talonmyburgh

@LarsAsplund I'm required to use older versions of VHDL (<2008) in order to use Vivado correctly. Early version do not allow for elements of an array to be unconstrained. So in my design we have an interface type with slv's in it that have bitwidths specified by a package. I cannot make use of this interface and pass down the bitwidths via generics.

dasHorst99

@dasHorst99

@LarsAsplund
Thank very much!

Unai Martinez-Corral

@umarcor

@talonmyburgh you can do VHDL 2008 -> ghdl synth -> VHDL 1993 -> Vivado, in order to use modern VHDL features without being limited by the poor support in Vivado.

Lars Asplund

@LarsAsplund

@talonmyburgh Ok, I see. What you have is basically several different but similar projects since the source code differs. If the package is a global common package it sounds like many files would depend on it and a lot of time would be spent on recompiling. If that is the case I would consider having different output paths for the different VUnit runs. One project has all the tests and the other project only have the tests with different widths.

Richard Head

@trickyhead_gitlab

@talonmyburgh What version of Vivado are you using? Vivado has very good synthesis of VHDL 2008 as of v2019.2. Unconstrained arrays have been working since before this.

Just dont bother with the simulator

Talon

@talonmyburgh

Thanks @LarsAsplund. Basically 2 run.py scripts with different outputs.

@trickyhead_gitlab, I unfortunately have to support a few versions of Vivado - from 2018 to 2021 (this is an open-source project with older hardware support required... sometimes as far back as ISE). We also support older versions of Quartus.

Thanks @umarcor , I must really look into this more. At present, CASPER (which is the organisation I am doing this HDL work for) compiles via Simulink (system generator and dsp builder). As a result, this move would require quite a bit of work but I'll bare it in mind.

Unai Martinez-Corral

@umarcor

@talonmyburgh is it https://github.com/casper-astro ?

I'm familiar with System Generator and, to a less extent, with HDL Verifier. I agree that introducing GHDL in that pipeline is not straightforward. However, it's something I want to document in the mid term.

I did use GHDL in a Vivado HLS -> VHDL -> GHDL -> Vivado workflow, which is not very different. But we are missing the tooling for the plumbing (see https://edaa-org.github.io/).

Talon

@talonmyburgh

Hi @umarcor that is it. A better starting place for information on the community is here.

Essentially, CASPER aims to provide a simple way for radio astronomers to deploy DSP backends for their radio telescopes. To keep things high-level, CASPER has some engineers in it's community create IP blocks in Simulink (or in my case HDL) for the scientists to make use of in the Simulink environment. The designs that the scientists create are largely simplified as Memory mapping, interfaces and ethernet cores are largely handled by the CASPER toolflow.

Up until now, all DSP for CASPER has been designed in Simulink. The several downsides to this are:

The cores are hard to regression test - and as such are not.
CASPER as an open source community is tied to a proprietary software (MATLAB & Simulink).
We must use Vivado/Quartus to synth/imp our designs.

Over the years CASPER has made efforts to move away from Simulink and the latest effort has been my HDL work to have an HDL FFT and Polyphase Filterbank (see here. Having our cores in HDL allows us to regression test with VUnit (which you will see I have working finally). It also lets us explore other graphical frontends to wrap the cores in (though we have wrapped them in Simulink for backwards compatibility). Finally, it allows us to be vendor agnostic (not being tied to System Generator or DSP builder for the synth/imp of our DSP).

Eventually, our goal is for users to choose a graphical frontend from a host of offered ones, include our HDL library, create their design at a high level and deploy to a wide range of hardware by way of a synth/imp of their choice.

Sorry for the long message.

Unai Martinez-Corral

@umarcor

@talonmyburgh no need to be sorry. That's pretty exciting indeed! If you went through my history/profile in GitHub, you would find out that I joined the open source HDL/EDA community some years ago, with the horizon of having an open source alternative to the Mathworks-Siemens-Xilinx workflow. That's 100% the same use case as yours. My background is control systems (PID, MPC) and feedforward neural networks; i.e. DSP and linear algebra.
My motivation for searching an open source alternative was the lack of VHDL 2008 support, and the limited black-box approach of System Generator.
Five years ago, GHDL's 2008 support was not there yet, and HDL Verifier was not a thing. Therefore, the ecosystem is different today, but there is still place for an open source alternative. Particularly, HDL Verifier depends on UVM and SV's DPI-C, so it is not usable with open source or free tier licenses.
Let me gather some references that might be interesting for you:

Unai Martinez-Corral

@umarcor

https://github.com/ghdl/ghdl-cosim (I have the perception that you might know Ross Donnachie? Maybe you are colleagues?)
- Work towards an standard direct co-simulation interface in VHDL 202X: https://github.com/VHDL/Compliance-Tests/tree/master/cosim
- Note the hdltypes and pyhdltypes from @ktbarrett, which are related to the management of (bit) arrays in cocotb. That's not exactly part of the co-simulation interface, but it's very tightly related.
https://umarcor.github.io/osvb/notebook/fpconv.html: exploring alternatives to data type analysis features in Mathworks' Fixed-Point Toolbox.
- I need to update it to explain the VPI alternative: https://github.com/umarcor/osvb/tree/main/fpconv
Using VHPIDIRECT for synthesis (umarcor/umarcor#1): i.e. call Octave/Matlab/Python functions which compute parameters for synthesis.
https://umarcor.github.io/hwstudio/: proof of concept of a GUI based on the Godot open source 2D/3D game engine.
- The actually interesting content of hwstudio is the docs: https://umarcor.github.io/hwstudio/doc/
- Go see the GNURadio paragraph in the References: https://umarcor.github.io/hwstudio/doc/#_references
  - Very precisely: https://github.com/gnuradio/gr-verilog

I believe we can achieve that with VHDL/GHDL as well, and we can "freely" combine Verilog and/or VHDL modules with software blocks.

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