user_lengthand all other parameters.
I have another question. This time about the pop function from AXI stream.
I want to push and pop the tuser flag on axi stream. Push works fine, but I can't pop it.
It gives me the following error, but I don' t know why.
(vcom-1600) No feasible entries for subprogram "pop_axi_stream".
I configured the master and slave the same way:
constant master_axi_stream_bus : axi_stream_master_t := new_axi_stream_master( data_length => data_width, user_length => tuser_width ); constant slave_axi_stream_bus : axi_stream_slave_t := new_axi_stream_slave( data_length => data_width, user_length => tuser_width );
variable user : std_logic_vector(tuser_width-1 downto 0);
And my pop function looks like this:
pop_axi_stream(net, slave_axi_stream_bus, tdata => received_data, tlast => last, tuser => user);
Without the tuser all works fine.
Does anyone perhaps have a suggestion?
so I have what is possibly a very silly query but I am unsure how to go about solving it all the same.
I have a vhdl pkg with constants that govern the slv bit widths in my design. I cannot pass these bitwidths down via generics as these widths are specifications for bitwidths in an slv array.
The majority of my tests run with one bit width, but I have a few cases where I require a different one.
I want to know whether I can have a set up as follows:
Is this possible? I've not seen any way to remove tb configurations.
Hi @umarcor that is it. A better starting place for information on the community is here.
Essentially, CASPER aims to provide a simple way for radio astronomers to deploy DSP backends for their radio telescopes. To keep things high-level, CASPER has some engineers in it's community create IP blocks in Simulink (or in my case HDL) for the scientists to make use of in the Simulink environment. The designs that the scientists create are largely simplified as Memory mapping, interfaces and ethernet cores are largely handled by the CASPER toolflow.
Up until now, all DSP for CASPER has been designed in Simulink. The several downsides to this are:
Over the years CASPER has made efforts to move away from Simulink and the latest effort has been my HDL work to have an HDL FFT and Polyphase Filterbank (see here. Having our cores in HDL allows us to regression test with VUnit (which you will see I have working finally). It also lets us explore other graphical frontends to wrap the cores in (though we have wrapped them in Simulink for backwards compatibility). Finally, it allows us to be vendor agnostic (not being tied to System Generator or DSP builder for the synth/imp of our DSP).
Eventually, our goal is for users to choose a graphical frontend from a host of offered ones, include our HDL library, create their design at a high level and deploy to a wide range of hardware by way of a synth/imp of their choice.
Sorry for the long message.
I believe we can achieve that with VHDL/GHDL as well, and we can "freely" combine Verilog and/or VHDL modules with software blocks.
We've had meetings with GNURadio before to discuss making use of their GNURadio Companion for a Simulink Replacement.
As for MATLAB's FixPoint ToolBox, for my MSc I wrote a replacement (somewhat) in Python and am now converting it to Julia for speed. I used it for Fixpoint analysis FFT's on FPGA hardware (compiled through System Generator).
I'll inspect your GitHub closely, I'd looked at hwstudio before but didnt understand it.
Thanks a ton for all these references I'll look into them.
You should attend our next CASPER meeting/conference or you myself and Ross should meet sometime.
I experience a problems with use clause for locally declared packages.
architecture tb of tb_spi is
package sb_rl_data is new bitvis_vip_scoreboard.generic_sb_pkg
generic map (t_element => t_RL_ARRAY,
element_match => slv_array_match,
to_string_element => to_string);
shared variable SB_RL : sb_rl_data.t_generic_sb;
In this case the use clause do not starts with library name but with simple identifier. The problem is I'm getting the following warning :
WARNING - /tb/tb_data_switch.vhd: failed to find library 'sb_rl_data'
I expect this could also cause incorrect compilation order too.
Is this problem known or should I file a bug report?
Thanks for help
I am using vunit now for some weeks now and slowly get a hang of it. Nice little functions are included especially for the integer_array type. Very neet and usefull!
There is now one little task that I have solved but I am curious if some one could say me if there is a function for this or can maybe explain me how it can be done easier.
My task is that I want to read a bmp file. So I read the whole data by using the load_raw function. But I only want a chunk of that data for example the head. Also it must be considered that the bytes are ordered in little endian.
impure function get_header_info(input_arr : integer_array_t; a : natural; b : natural) return natural is variable output_value_vector : std_logic_vector(31 downto 0) := (others => '0'); variable output_value_int : natural := 0; variable output_arr : integer_array_t := new_1d(4, 8, false); begin for x in a to b loop set(output_arr, x-a, get(input_arr, x)); end loop; output_value_vector := std_logic_vector(to_unsigned(get(output_arr, 3), 8)) & std_logic_vector(to_unsigned(get(output_arr, 2), 8)) & std_logic_vector(to_unsigned(get(output_arr, 1), 8)) & std_logic_vector(to_unsigned(get(output_arr, 0), 8)); output_value_int := to_integer(unsigned(output_value_vector)); return output_value_int; end function;
This is not the best code, so maybe there is a better or more convinient way to do this?
function swap(value : std_logic_vector; size : positive := 8) return std_logic_vector is constant segments : natural := value'length / size; variable result : std_logic_vector(value'length - 1 downto 0); begin for i in 0 to segments - 1 loop result((segments - i) * size - 1 downto (segments - i - 1) * size) := value((i + 1) * size - 1 downto i * size); end loop; return result; end function;