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Ha, I know std_logic_vectors. I am not so dump after all. ;) Now I am checking slvs was the abbreviation.
My first attempt was exactly this approach, but my code was big and not nice. Now with the vunit functions it is a lot smaller and not so complicated. Therefore I accept the integer conversion with the integer_array.
architecture tb of tb_spi is .... package sb_rl_data is new bitvis_vip_scoreboard.generic_sb_pkg generic map (t_element => t_RL_ARRAY, element_match => slv_array_match, to_string_element => to_string); use sb_rl_data.all; shared variable SB_RL : sb_rl_data.t_generic_sb; ... begin
The reason I ask is because I read in an image file (bmp) with the save_raw() function.
shared variable t_whole_image_data : integer_array_t; t_whole_image_data := load_raw(g_image_filename, 8, false);
Then I ask with the length() for the length
info("length: " & to_string(length(t_whole_image_data)));
and get the result 78840, but my hex editor says that the data goes from 0 to 78840.
@/all Following a discussion in another gitter room we added a feature which generates an error if you have a directly instantiated entity like this:
thing_inst: entity lib.thing port map ( clk => clk, rst => rst, q => q);
and more than one architecture specified. VHDL rules dictates that the latest successfully compiled architecture shall be used but since you do not (normally) control what order code is compiled this results in an arbitrary selection of architecture. Now you will have an error message like this:
ERROR - Ambiguous direct entity instantiation of lib.thing in C:\examples\ambiguous_architecture\system.vhd. Remove all but one architecture or specify one of: 1. behavioral (C:\examples\ambiguous_architecture\thing_behavioral.vhd) 2. rtl (C:\examples\ambiguous_architecture\thing_rtl.vhd)
If you encounter this just follow the instructions, for example
thing_inst: entity lib.thing(rtl) port map ( clk => clk, rst => rst, q => q);
and the error will disappear.
add_dependencymethod but that is not a great solution. Your intent should be expressed in the code and not the in the build script. There are also limitation to what you can do with compile order. If you have several architectures in the same file you can't control order. If you have one instance using one architecture and another instance using the other then both will get the same. This is really a user mistake that VHDL pass silently. Now we have a safety mechanism preventing that.
I think your best bet is to turn off preprocessing and try it again. If that works, re-enable preprocessing and read through the preprocessed file to see if you can figure out what's going on. I can't help much unless you post the problem file before and after VUnit enabled it. I would also suggest using TerosHDL, ghdl_ls, or another VHDL LS that can check your syntax. Those will help uncover errors like this... Now onto some more context
You probably have a syntax error somewhere in that file. Mismatched parenthesis or begin/end were two common cases where I saw that error. To handle preprocessing, VUnit has to move the file to a new location and modify it to add line numbers etc. to the subprogram args. The feature is great and VUnit is nearly perfect from what I've seen at parsing/modifying... BUT, VUnit does not understand semantics (or anything I don't think, I'm pretty sure it uses pure regex parsing), so it'll happily make a modification even though the file has syntax issues. I can't blame it, it's the simulator's job to report errors in the code, VUnit is just the middle man. The simulator sees a critical issue with VUnit's modification because the arguments for the log subprograms aren't correct so it complains about those instead of the real syntax issues. Basically, VUnit unintentionally masks the real error. Maybe changing simulators will help if the other one reports more errors while analyzing the file, but that's a gamble.
I got burned so many times fixing syntax errors with preprocessed files only to see the same or similar error. After digging into them for longer than I'll admit, I found out I accidentally modified the preprocessed file instead of the source file when I found the problem. I don't use the preprocessing feature for this reason. It's great and works 100% of the time, but when your code isn't correct, it can be a huge pain to debug. I think I opened an issue a long time ago on GitHub, but I don't remember. That might have more info about my workaround if there was one.
I love having my logs tell me where a log message is, but until VHDL can provide the extra info like file and line num, it's more headache than it's worth. If you want that feature, check out ActiveHDL >12, RivieraPRO, or ask your simulator vendor to add VHDL2019 support. My workaround for this problem was to write better log messages in the first place, basically something that can be grepped easily. Reference https://github.com/google/styleguide/blob/gh-pages/pyguide.md#3102-error-messages
disclaimer not sure if VUnit supports 2019 so the above suggestion about that might not be feasible yet. I haven't been keeping up with the development for a long while.
I am struggling to set up VUnit in Ubuntu.
Does anyone uses it in Ubuntu environment?
Could that be related to the Python Paths? I have not changed anything in the Python Paths after installing VUnit.
When I try to run one of the examples from VUnit repository I get this:
WARNING - Option 'compile_builtins' of methods 'from_args' and 'from_argv' is deprecated.
In future releases, it will be removed and builtins will need to be added explicitly.
To prepare for upcoming changes, it is recommended to apply the following modifications in the run script now:
WARNING - Found no tests or test suite within /home/user/Documents/fpga/vunit/examples/vhdl/run/tb_with_lower_level_control.vhd
Compiling into vunit_lib: ../../../vunit/vhdl/string_ops/src/string_ops.vhd failed
=== Command used: ===
/usr/bin/ghdl -a --workdir=/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib --work=vunit_lib --std=08 -P/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib -P/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/lib /home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd
=== Command output: ===
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:12:10: unit "numeric_std" not found in library "ieee"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:99:22: no declaration for "unsigned"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:102:22: no declaration for "signed"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:101:12: redeclaration of function "to_integer_string" defined at line 98:12
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:108:22: no declaration for "unsigned"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:114:22: no declaration for "signed"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:113:12: redeclaration of function "to_nibble_string" defined at line 107:12
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:118:14: package "string_ops" was not analysed
Thanks for the support, at the moment I really was looking for a "Hello World" example to run with VUnit.