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  • 11:23
    mkuklewski commented #861
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  • Sep 01 13:55
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  • Aug 31 21:49
    LarsAsplund commented #859
Lars Asplund
@LarsAsplund
I'm noting that 1078 is not a multiple of 4 so if you read 32 bit chunks the problem may be there
dasHorst99
@dasHorst99
@LarsAsplund
You are right, but I am not always reading 4 bytes. In the header are also 2 byte fields. But I read the 1078 out of the header. I am not calculating them.
Patrick Lehmann
@Paebbels
@dasHorst99 Oh, t_whole_image_data is a protected type instance.
The t_ distracted me ...
then you need to implement a method in the protected type to get the inner value.
Lars Asplund
@LarsAsplund

@/all Following a discussion in another gitter room we added a feature which generates an error if you have a directly instantiated entity like this:

  thing_inst: entity lib.thing
    port map (
      clk => clk,
      rst => rst,
      q => q);

and more than one architecture specified. VHDL rules dictates that the latest successfully compiled architecture shall be used but since you do not (normally) control what order code is compiled this results in an arbitrary selection of architecture. Now you will have an error message like this:

  ERROR - Ambiguous direct entity instantiation of lib.thing in C:\examples\ambiguous_architecture\system.vhd.
  Remove all but one architecture or specify one of:
  1. behavioral (C:\examples\ambiguous_architecture\thing_behavioral.vhd)
  2. rtl (C:\examples\ambiguous_architecture\thing_rtl.vhd)

If you encounter this just follow the instructions, for example

  thing_inst: entity lib.thing(rtl)
    port map (
      clk => clk,
      rst => rst,
      q => q);

and the error will disappear.

Richard Head
@trickyhead_gitlab
Will this work if someone had all architectures in 1 file?
Lars Asplund
@LarsAsplund
Yes, the problem isn't that you have many architectures but that you're not specific about which you're referring to.
svenn71
@svenn71
"arbitrary selected architecture" sounds scary when doing asic design.
Richard Head
@trickyhead_gitlab
@svenn71 I assume its because vunit (and other tools) can determine the compile order for you. With your own scripts you can determine your own compile order
Lars Asplund
@LarsAsplund
@trickyhead_gitlab You can enforce the compile order of two files in VUnit with the add_dependency method but that is not a great solution. Your intent should be expressed in the code and not the in the build script. There are also limitation to what you can do with compile order. If you have several architectures in the same file you can't control order. If you have one instance using one architecture and another instance using the other then both will get the same. This is really a user mistake that VHDL pass silently. Now we have a safety mechanism preventing that.
svenn71
@svenn71
but in an asic project I am never alone, so there is seldom something called "my script" only "my code", and if "my code" is picking up the wrong architecture downstream, I would like to know that early
Lars Asplund
@LarsAsplund
True, and with VUnit you now have that early warning. Another safety measure , if you need multiple architectures, is to use namespaces more. You could for example compile behavioral, rtl, and gate-level models to different libraries.
svenn71
@svenn71
and then hope for the downstream asic workflow to support libraries :)
Lars Asplund
@LarsAsplund
Exactly!
nfrancque
@nfrancque
@LarsAsplund This warning only applies if vunit is provided multiple architectures of the same component, correct? We aren't forced to specify if only one architecture is available?
Lars Asplund
@LarsAsplund
@nfrancque Correct. It's only when there is more than one architecture this becomes a problem and only then we issue an error
if len(primary_unit.architecture_names) > 1:
  self._handle_ambiguous_architecture(source_file, ref, primary_unit)
Lars Asplund
@LarsAsplund
Note that there can still be two architectures in the compiled library but I think that might safe. Let's say you have a behavioral architecture and then add an rtl one without being specific in your instantiation. You will then get the error. If you decide to remove the addition of the behavioral architecture file in your run script the error will go away and the rtl model will be compiled. The behavioral model will still be in the library unless you did a clean compile but since the rtl architecture was compiled last it is the one used
nfrancque
@nfrancque
Yep that all makes sense to me. Personally don't use multiple architectures for much but the people I have seen use it usually leave it unspecified and then change their compile script depending on the target. For these people accidentally including both is almost always a problem, so might be worth adding an option to up it to an error and not allow compile? Doesn't affect me either way but if it did that would sound useful.
Lars Asplund
@LarsAsplund
This will raise a runtime error in Python so you have to fix it or VUnit won't proceed:
if len(primary_unit.architecture_names) > 1:
  self._handle_ambiguous_architecture(source_file, ref, primary_unit)
  raise RuntimeError(f"Ambiguous use of {ref.library}.{ref.design_unit}")
nfrancque
@nfrancque
Ah - perfect! Thanks
dpaul
@dpaul24
@all, First the silly question - Does VUnit based sim using ModelSim run successfully under a Linux Ubuntu Docker image?
Background: I have a Microchip Libero 2021.2 based project for which I run sim using VUnit and ModelSim. I use complete TCL mode. The VUnit based sim run perfectly under Windows10 and a real Linux Ubuntu machine. But the same script fails to run under a Linux Ubuntu docker image. I do not think this is a VUnit problem but has more to do with Libero. Has anyone experience in such a case?
dpaul
@dpaul24
fyi - In Linux I just take care of the paths, and it works. The original project was created on win10.
Adrian Byszuk
@abyszuk
@dpaul24 I have my whole CI setup in Gitlab using Docker images of GHDL/Modelsim with VUnit and it works just fine. There are a few differences wrt. what you ask:
  • Docker image is based on CentOS 8
  • Xilinx Unisim libraries instead of Libero
\o_O/
@nanoeng
@GlenNicholls I came across the same issue @Ahmad-Zaklouta described in his posting on October the 5th. Do you happen to have any advice about what could be wrong with our set up?
GlenNicholls
@GlenNicholls

I think your best bet is to turn off preprocessing and try it again. If that works, re-enable preprocessing and read through the preprocessed file to see if you can figure out what's going on. I can't help much unless you post the problem file before and after VUnit enabled it. I would also suggest using TerosHDL, ghdl_ls, or another VHDL LS that can check your syntax. Those will help uncover errors like this... Now onto some more context

You probably have a syntax error somewhere in that file. Mismatched parenthesis or begin/end were two common cases where I saw that error. To handle preprocessing, VUnit has to move the file to a new location and modify it to add line numbers etc. to the subprogram args. The feature is great and VUnit is nearly perfect from what I've seen at parsing/modifying... BUT, VUnit does not understand semantics (or anything I don't think, I'm pretty sure it uses pure regex parsing), so it'll happily make a modification even though the file has syntax issues. I can't blame it, it's the simulator's job to report errors in the code, VUnit is just the middle man. The simulator sees a critical issue with VUnit's modification because the arguments for the log subprograms aren't correct so it complains about those instead of the real syntax issues. Basically, VUnit unintentionally masks the real error. Maybe changing simulators will help if the other one reports more errors while analyzing the file, but that's a gamble.

I got burned so many times fixing syntax errors with preprocessed files only to see the same or similar error. After digging into them for longer than I'll admit, I found out I accidentally modified the preprocessed file instead of the source file when I found the problem. I don't use the preprocessing feature for this reason. It's great and works 100% of the time, but when your code isn't correct, it can be a huge pain to debug. I think I opened an issue a long time ago on GitHub, but I don't remember. That might have more info about my workaround if there was one.

I love having my logs tell me where a log message is, but until VHDL can provide the extra info like file and line num, it's more headache than it's worth. If you want that feature, check out ActiveHDL >12, RivieraPRO, or ask your simulator vendor to add VHDL2019 support. My workaround for this problem was to write better log messages in the first place, basically something that can be grepped easily. Reference https://github.com/google/styleguide/blob/gh-pages/pyguide.md#3102-error-messages

disclaimer not sure if VUnit supports 2019 so the above suggestion about that might not be feasible yet. I haven't been keeping up with the development for a long while.

Lars Asplund
@LarsAsplund
@GlenNicholls @nanoeng Support for finding line and file location was the reason I joined the work with VHDL 2019. Riviera-PRO supports this so if you use that simulator with the 2019 standard you get location without preprocessing. Active-HDL also supports but there was a bug which caused this feature to fail. Workaround is in the pipe.
Note that RPRO requires your code (not VUnit) to be debug complied for the feature to work.
sh-vlad
@sh-vlad
Hi. I was included to a project where vunit is used. There is huge legacy in the project so I faced some issues and a russian local community advised me to try ask my question here. I have thousands of rtl sources and thousand of vunit testcases. Imagine I modified a rtl module how can I find all tests which check the module? Now I use flag "--list" but it doesn't work when a rtl module and a test has different names.
\o_O/
@nanoeng
@GlenNicholls @LarsAsplund thanks for the detailed replies!
erik
@eccornelsen

Hi there,
I am struggling to set up VUnit in Ubuntu.
Does anyone uses it in Ubuntu environment?
Could that be related to the Python Paths? I have not changed anything in the Python Paths after installing VUnit.
When I try to run one of the examples from VUnit repository I get this:

~/Documents/fpga/vunit/examples/vhdl/run$ python3 run.py

WARNING - Option 'compile_builtins' of methods 'from_args' and 'from_argv' is deprecated.
In future releases, it will be removed and builtins will need to be added explicitly.
To prepare for upcoming changes, it is recommended to apply the following modifications in the run script now:

  • Use from_argv(compile_builtins=False) or from_args(compile_builtins=False).
  • Add an explicit call to 'add_vhdl_builtins'.

See VUnit/vunit#777.

===========================================================================
WARNING - Found no tests or test suite within /home/user/Documents/fpga/vunit/examples/vhdl/run/tb_with_lower_level_control.vhd
Compiling into vunit_lib: ../../../vunit/vhdl/string_ops/src/string_ops.vhd failed
=== Command used: ===
/usr/bin/ghdl -a --workdir=/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib --work=vunit_lib --std=08 -P/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib -P/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/lib /home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd

=== Command output: ===
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:12:10: unit "numeric_std" not found in library "ieee"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:99:22: no declaration for "unsigned"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:102:22: no declaration for "signed"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:101:12: redeclaration of function "to_integer_string" defined at line 98:12
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:108:22: no declaration for "unsigned"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:114:22: no declaration for "signed"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:113:12: redeclaration of function "to_nibble_string" defined at line 107:12
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:118:14: package "string_ops" was not analysed

Compile failed

Thanks for the support, at the moment I really was looking for a "Hello World" example to run with VUnit.

Colin Marquardt
@cmarqu
@eccornelsen https://gitter.im/VUnit/vunit?at=5ea1ae75501f8f72a5fcca06 describes your problem and suggests some things to try
erik
@eccornelsen

Thanks @cmarqu ,
I did some checks as in the post but still same error.
Here some findings if it may help:

  1. Check /usr/lib/ghld
    /usr/lib/ghdl$ /usr/bin/ghdl
    /usr/bin/ghdl-mcode:error: missing command, try /usr/bin/ghdl-mcode --help

  2. Check /usr/lib/ghdl:
    /usr/lib/ghdl$ ls -1a
    .
    ..
    include
    mcode
    src

ieee is missing here

  1. Check /usr/lib/ghdl/src:
    /usr/lib/ghdl/src$ ls -1a -R
    .:
    .
    ..
    openieee
    std
    synopsys

./openieee:
.
..
math_real-body.vhdl
math_real.vhdl
upf-body.vhdl
upf.vhdl
v08
v87
v93

./openieee/v08:
.
..
std_logic_1164-body.vhdl
std_logic_1164.vhdl

./openieee/v87:
.
..
numeric_bit-body.vhdl
numeric_bit.vhdl
numeric_std-body.vhdl
numeric_std.vhdl
std_logic_1164-body.vhdl
std_logic_1164.vhdl

./openieee/v93:
.
..
numeric_bit-body.vhdl
numeric_bit.vhdl
numeric_std-body.vhdl
numeric_std.vhdl
std_logic_1164-body.vhdl
std_logic_1164.vhdl

./std:
.
..
env-body.vhdl
env.vhdl
v08
v87
v93

./std/v08:
.
..
standard.vhdl
textio-body.vhdl
textio.vhdl

./std/v87:
.
..
standard.vhdl
textio-body.vhdl
textio.vhdl

./std/v93:
.
..
standard.vhdl
textio-body.vhdl
textio.vhdl

./synopsys:
.
..
std_logic_arith.vhdl
std_logic_misc-body.vhdl
std_logic_misc.vhdl
std_logic_signed.vhdl
std_logic_textio.vhdl
std_logic_unsigned.vhdl
v08

./synopsys/v08:
.
..

  1. ghdl version: 0.37

  2. $PATH:
    bash: /home/erik/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin: No such file or directory

/Documents/fpga/vunit/examples/vhdl/run$ python3 run.py

Compiling into vunit_lib: ../../../vunit/vhdl/string_ops/src/string_ops.vhd failed
=== Command used: ===
/usr/bin/ghdl -a --workdir=/home/erik/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib --work=vunit_lib --std=08 -P/home/erik/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib -P/home/erik/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/lib --ieee=synopsys -frelaxed-rules /home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd

=== Command output: ===
/usr/bin/ghdl-mcode:warning: ieee library directory '/usr/lib/ghdl/mcode/vhdl/synopsys/v08/' not found
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:12:10: unit "numeric_std" not found in library "ieee"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:99:22: no declaration for "unsigned"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:102:22: no declaration for "signed"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:101:12: redeclaration of function "to_integer_string" defined at line 98:12
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:108:22: no declaration for "unsigned"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:114:22: no declaration for "signed"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:113:12: redeclaration of function "to_nibble_string" defined at line 107:12
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:118:14: package "string_ops" was not analysed

Compile failed

Could that be some missing dependencies or something wrong with the $PATH?
Thanks

Colin Marquardt
@cmarqu
@eccornelsen I think the best move is to upgrade your old 0.37 version to 1.0: https://ghdl.github.io/ghdl/getting.html
erik
@eccornelsen
thanks for the advice s @cmarqu , upgraded from 0.37 to GHDL 2.0.0-dev and now the examples are running as expected
dasHorst99
@dasHorst99

Hi,
can someone tell how I set the compile option properly to VHDL 2019? I can't figure it out from the descriptions of the compile options in the docs.

best regards

Richard Head
@trickyhead_gitlab
@dasHorst99 Which tool are you using? no tools currently have any 2019 support (other than Aldec Tools, where support is basic)
dasHorst99
@dasHorst99
Modelsim 2021.2.
But you are right. I thought that Modelsim will defently supports 2019 but I will check.
Richard Head
@trickyhead_gitlab
no - I raised a ticket about it 4 weeks ago, and their response was "We are thinking about adding basic support in the future"
so dont hold your breath. Aldec are going full steam ahead with support and ActiveHDL 13.0 will support generic protected types
as well as the more complex generic types
dasHorst99
@dasHorst99
This is disappointing news. That you for your fast and good reply Richard!
Richard Head
@trickyhead_gitlab
Raise a ticket with seimens . The more demand may lead to quicker support
FYI - most (if not all) tools do not even have full 2008 feature support
Lars Asplund
@LarsAsplund
@dasHorst99 When 2019 support is added to Modelsim we will also enable you to set it through VUnit without figuring out the compile option. You can set VHDL standard when adding source code in your run script or you can use the VUNIT_VHDL_STANDARD environment variable to change the global default. The default is 2008 today. If you try this with ModelSim you will get an error saying that 2019 isn't support.
dasHorst99
@dasHorst99
@LarsAsplund Ok, good to know. Thanks you for the for the additional Information.
Jim Lewis
@JimLewis
@trickyhead_gitlab WRT VHDL-2019, big thing I see missing in RivieraPRO is unspecified types and related - usage of unspecified types on interfaces - particularly subprograms. Yes it is a big one, but they have implemented other big ones related to protected types and interfaces.
Richard Head
@trickyhead_gitlab
@JimLewis Maybe they just need some use cases? I provided some examples for generic protected types and more complicated generic types and ways I wanted to use them
Jim Lewis
@JimLewis
@trickyhead_gitlab Perhaps I need to do a linkedin post on the VHDL-2019 examples I did for my VHDL-2019 presentations through Aldec. I included examples with it. The examples are here: https://gitlab.com/synthworks/VHDL_2019
GlenNicholls
@GlenNicholls

I'm trying to cross-reference vunit package in my Sphinx documentation using intersphinx_mapping. Should I be setting vunit to something else to get this to work?

intersphinx_mapping = {
    'vunit': ('https://vunit.github.io/', None),
    'https://docs.python.org/': None
}

Basically, when I cross-reference

:class:`vunit.VUnit`

or

:mod:`vunit`

Sphinx doesn't hot-link to anything.

When I use that link, Sphinx doesn't issue any warnings/errors about it so I'm not sure if I am pointing to the correct link, but my documentation doesn't actually create a link for those references like it does with other packages.