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  • Nov 25 12:43
    eine milestoned #839
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    Fixes #874 (compare)

  • Nov 14 10:53

    LarsAsplund on master

    Enable VHDL-2019 for Active-HDL… (compare)

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\o_O/
@nanoeng
@GlenNicholls I came across the same issue @Ahmad-Zaklouta described in his posting on October the 5th. Do you happen to have any advice about what could be wrong with our set up?
GlenNicholls
@GlenNicholls

I think your best bet is to turn off preprocessing and try it again. If that works, re-enable preprocessing and read through the preprocessed file to see if you can figure out what's going on. I can't help much unless you post the problem file before and after VUnit enabled it. I would also suggest using TerosHDL, ghdl_ls, or another VHDL LS that can check your syntax. Those will help uncover errors like this... Now onto some more context

You probably have a syntax error somewhere in that file. Mismatched parenthesis or begin/end were two common cases where I saw that error. To handle preprocessing, VUnit has to move the file to a new location and modify it to add line numbers etc. to the subprogram args. The feature is great and VUnit is nearly perfect from what I've seen at parsing/modifying... BUT, VUnit does not understand semantics (or anything I don't think, I'm pretty sure it uses pure regex parsing), so it'll happily make a modification even though the file has syntax issues. I can't blame it, it's the simulator's job to report errors in the code, VUnit is just the middle man. The simulator sees a critical issue with VUnit's modification because the arguments for the log subprograms aren't correct so it complains about those instead of the real syntax issues. Basically, VUnit unintentionally masks the real error. Maybe changing simulators will help if the other one reports more errors while analyzing the file, but that's a gamble.

I got burned so many times fixing syntax errors with preprocessed files only to see the same or similar error. After digging into them for longer than I'll admit, I found out I accidentally modified the preprocessed file instead of the source file when I found the problem. I don't use the preprocessing feature for this reason. It's great and works 100% of the time, but when your code isn't correct, it can be a huge pain to debug. I think I opened an issue a long time ago on GitHub, but I don't remember. That might have more info about my workaround if there was one.

I love having my logs tell me where a log message is, but until VHDL can provide the extra info like file and line num, it's more headache than it's worth. If you want that feature, check out ActiveHDL >12, RivieraPRO, or ask your simulator vendor to add VHDL2019 support. My workaround for this problem was to write better log messages in the first place, basically something that can be grepped easily. Reference https://github.com/google/styleguide/blob/gh-pages/pyguide.md#3102-error-messages

disclaimer not sure if VUnit supports 2019 so the above suggestion about that might not be feasible yet. I haven't been keeping up with the development for a long while.

Lars Asplund
@LarsAsplund
@GlenNicholls @nanoeng Support for finding line and file location was the reason I joined the work with VHDL 2019. Riviera-PRO supports this so if you use that simulator with the 2019 standard you get location without preprocessing. Active-HDL also supports but there was a bug which caused this feature to fail. Workaround is in the pipe.
Note that RPRO requires your code (not VUnit) to be debug complied for the feature to work.
sh-vlad
@sh-vlad
Hi. I was included to a project where vunit is used. There is huge legacy in the project so I faced some issues and a russian local community advised me to try ask my question here. I have thousands of rtl sources and thousand of vunit testcases. Imagine I modified a rtl module how can I find all tests which check the module? Now I use flag "--list" but it doesn't work when a rtl module and a test has different names.
\o_O/
@nanoeng
@GlenNicholls @LarsAsplund thanks for the detailed replies!
erik
@eccornelsen

Hi there,
I am struggling to set up VUnit in Ubuntu.
Does anyone uses it in Ubuntu environment?
Could that be related to the Python Paths? I have not changed anything in the Python Paths after installing VUnit.
When I try to run one of the examples from VUnit repository I get this:

~/Documents/fpga/vunit/examples/vhdl/run$ python3 run.py

WARNING - Option 'compile_builtins' of methods 'from_args' and 'from_argv' is deprecated.
In future releases, it will be removed and builtins will need to be added explicitly.
To prepare for upcoming changes, it is recommended to apply the following modifications in the run script now:

  • Use from_argv(compile_builtins=False) or from_args(compile_builtins=False).
  • Add an explicit call to 'add_vhdl_builtins'.

See VUnit/vunit#777.

===========================================================================
WARNING - Found no tests or test suite within /home/user/Documents/fpga/vunit/examples/vhdl/run/tb_with_lower_level_control.vhd
Compiling into vunit_lib: ../../../vunit/vhdl/string_ops/src/string_ops.vhd failed
=== Command used: ===
/usr/bin/ghdl -a --workdir=/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib --work=vunit_lib --std=08 -P/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib -P/home/user/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/lib /home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd

=== Command output: ===
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:12:10: unit "numeric_std" not found in library "ieee"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:99:22: no declaration for "unsigned"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:102:22: no declaration for "signed"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:101:12: redeclaration of function "to_integer_string" defined at line 98:12
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:108:22: no declaration for "unsigned"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:114:22: no declaration for "signed"
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:113:12: redeclaration of function "to_nibble_string" defined at line 107:12
/home/user/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:118:14: package "string_ops" was not analysed

Compile failed

Thanks for the support, at the moment I really was looking for a "Hello World" example to run with VUnit.

Colin Marquardt
@cmarqu
@eccornelsen https://gitter.im/VUnit/vunit?at=5ea1ae75501f8f72a5fcca06 describes your problem and suggests some things to try
erik
@eccornelsen

Thanks @cmarqu ,
I did some checks as in the post but still same error.
Here some findings if it may help:

  1. Check /usr/lib/ghld
    /usr/lib/ghdl$ /usr/bin/ghdl
    /usr/bin/ghdl-mcode:error: missing command, try /usr/bin/ghdl-mcode --help

  2. Check /usr/lib/ghdl:
    /usr/lib/ghdl$ ls -1a
    .
    ..
    include
    mcode
    src

ieee is missing here

  1. Check /usr/lib/ghdl/src:
    /usr/lib/ghdl/src$ ls -1a -R
    .:
    .
    ..
    openieee
    std
    synopsys

./openieee:
.
..
math_real-body.vhdl
math_real.vhdl
upf-body.vhdl
upf.vhdl
v08
v87
v93

./openieee/v08:
.
..
std_logic_1164-body.vhdl
std_logic_1164.vhdl

./openieee/v87:
.
..
numeric_bit-body.vhdl
numeric_bit.vhdl
numeric_std-body.vhdl
numeric_std.vhdl
std_logic_1164-body.vhdl
std_logic_1164.vhdl

./openieee/v93:
.
..
numeric_bit-body.vhdl
numeric_bit.vhdl
numeric_std-body.vhdl
numeric_std.vhdl
std_logic_1164-body.vhdl
std_logic_1164.vhdl

./std:
.
..
env-body.vhdl
env.vhdl
v08
v87
v93

./std/v08:
.
..
standard.vhdl
textio-body.vhdl
textio.vhdl

./std/v87:
.
..
standard.vhdl
textio-body.vhdl
textio.vhdl

./std/v93:
.
..
standard.vhdl
textio-body.vhdl
textio.vhdl

./synopsys:
.
..
std_logic_arith.vhdl
std_logic_misc-body.vhdl
std_logic_misc.vhdl
std_logic_signed.vhdl
std_logic_textio.vhdl
std_logic_unsigned.vhdl
v08

./synopsys/v08:
.
..

  1. ghdl version: 0.37

  2. $PATH:
    bash: /home/erik/.local/bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin:/usr/games:/usr/local/games:/snap/bin: No such file or directory

/Documents/fpga/vunit/examples/vhdl/run$ python3 run.py

Compiling into vunit_lib: ../../../vunit/vhdl/string_ops/src/string_ops.vhd failed
=== Command used: ===
/usr/bin/ghdl -a --workdir=/home/erik/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib --work=vunit_lib --std=08 -P/home/erik/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/vunit_lib -P/home/erik/Documents/fpga/vunit/examples/vhdl/run/vunit_out/ghdl/libraries/lib --ieee=synopsys -frelaxed-rules /home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd

=== Command output: ===
/usr/bin/ghdl-mcode:warning: ieee library directory '/usr/lib/ghdl/mcode/vhdl/synopsys/v08/' not found
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:12:10: unit "numeric_std" not found in library "ieee"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:99:22: no declaration for "unsigned"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:102:22: no declaration for "signed"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:101:12: redeclaration of function "to_integer_string" defined at line 98:12
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:108:22: no declaration for "unsigned"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:114:22: no declaration for "signed"
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:113:12: redeclaration of function "to_nibble_string" defined at line 107:12
/home/erik/Documents/fpga/vunit/vunit/vhdl/string_ops/src/string_ops.vhd:118:14: package "string_ops" was not analysed

Compile failed

Could that be some missing dependencies or something wrong with the $PATH?
Thanks

Colin Marquardt
@cmarqu
@eccornelsen I think the best move is to upgrade your old 0.37 version to 1.0: https://ghdl.github.io/ghdl/getting.html
erik
@eccornelsen
thanks for the advice s @cmarqu , upgraded from 0.37 to GHDL 2.0.0-dev and now the examples are running as expected
dasHorst99
@dasHorst99

Hi,
can someone tell how I set the compile option properly to VHDL 2019? I can't figure it out from the descriptions of the compile options in the docs.

best regards

Richard Head
@trickyhead_gitlab
@dasHorst99 Which tool are you using? no tools currently have any 2019 support (other than Aldec Tools, where support is basic)
dasHorst99
@dasHorst99
Modelsim 2021.2.
But you are right. I thought that Modelsim will defently supports 2019 but I will check.
Richard Head
@trickyhead_gitlab
no - I raised a ticket about it 4 weeks ago, and their response was "We are thinking about adding basic support in the future"
so dont hold your breath. Aldec are going full steam ahead with support and ActiveHDL 13.0 will support generic protected types
as well as the more complex generic types
dasHorst99
@dasHorst99
This is disappointing news. That you for your fast and good reply Richard!
Richard Head
@trickyhead_gitlab
Raise a ticket with seimens . The more demand may lead to quicker support
FYI - most (if not all) tools do not even have full 2008 feature support
Lars Asplund
@LarsAsplund
@dasHorst99 When 2019 support is added to Modelsim we will also enable you to set it through VUnit without figuring out the compile option. You can set VHDL standard when adding source code in your run script or you can use the VUNIT_VHDL_STANDARD environment variable to change the global default. The default is 2008 today. If you try this with ModelSim you will get an error saying that 2019 isn't support.
dasHorst99
@dasHorst99
@LarsAsplund Ok, good to know. Thanks you for the for the additional Information.
Jim Lewis
@JimLewis
@trickyhead_gitlab WRT VHDL-2019, big thing I see missing in RivieraPRO is unspecified types and related - usage of unspecified types on interfaces - particularly subprograms. Yes it is a big one, but they have implemented other big ones related to protected types and interfaces.
Richard Head
@trickyhead_gitlab
@JimLewis Maybe they just need some use cases? I provided some examples for generic protected types and more complicated generic types and ways I wanted to use them
Jim Lewis
@JimLewis
@trickyhead_gitlab Perhaps I need to do a linkedin post on the VHDL-2019 examples I did for my VHDL-2019 presentations through Aldec. I included examples with it. The examples are here: https://gitlab.com/synthworks/VHDL_2019
GlenNicholls
@GlenNicholls

I'm trying to cross-reference vunit package in my Sphinx documentation using intersphinx_mapping. Should I be setting vunit to something else to get this to work?

intersphinx_mapping = {
    'vunit': ('https://vunit.github.io/', None),
    'https://docs.python.org/': None
}

Basically, when I cross-reference

:class:`vunit.VUnit`

or

:mod:`vunit`

Sphinx doesn't hot-link to anything.

When I use that link, Sphinx doesn't issue any warnings/errors about it so I'm not sure if I am pointing to the correct link, but my documentation doesn't actually create a link for those references like it does with other packages.
Lukas Vik
@LukasVik

@GlenNicholls Running

python -m sphinx.ext.intersphinx https://vunit.github.io/objects.inv

shows that names that are available. I just tested with

 :class:`vunit.ui.VUnit`

and it works well for me!

Peter Uran
@peteruran

Hello. I'm getting a "Subprogram check_equal is ambiguous" error, followed by an enormous wall of text when trying to compare an slv popped from a queue_t with a string literal.
check_equal(pop_std_ulogic_vector(tx_queue), x"CA", "Check byte 1");

Any suggestions on this? I see that the tb_queue in the VUnit GitHub repo uses assert statements for this instead. Why is that, and are there any downsides?
https://github.com/VUnit/vunit/blob/master/vunit/vhdl/data_types/test/tb_queue.vhd

nfrancque
@nfrancque
@peteruran I believe the literal you provided is ambiguous - it could be a std_logic_vector, unsigned, etc. Try storing it in a variable first.
GlenNicholls
@GlenNicholls
Ahh, silly mistake. Thanks @LukasVik
Lars Asplund
@LarsAsplund
@peteruran You can also do std_logic_vector'("CA")
sschmitz86
@sschmitz86
i wonder , is someone using vunit with ghdl and code coverage ? I use the ghdl/vunit:gcc-master docker container. It should support code coverage. After i got 0% code coverage on all files in my project i did try the coverage example from vunit. Same here, 0% code coverage
Gitter1510
@Gitter1510

Hi guys
for a student project about verification I wanted to do some tests of a DUT using vunit. My goal is to perform the results of the stimulation with a testbench with the measurement results of a LogicAnalyser of the same system. For this I am looking for a way to generate some kind of result table with the corresponding states and timings of my variables when testing with vunit. Does anyone have an idea ?
I hope I have formulated my problem halfway clearly. I am still completely new in the area of HDL and testing, should I say something wrong please excuse me :)

Translated with www.DeepL.com/Translator (free version)

dpaul
@dpaul24
@Gitter1510 , No not completely clear in what you want to do, but this is what VUnit does - "It features the functionality needed to realize continuous and automated testing of your HDL code. VUnit doesn’t replace but rather complements traditional testing methodologies by supporting a “test early and often” approach through automation." Your testbench is still dictates what you want to do and how do you want to project the simulation results.
Having said that, from what I have understood from your post, do you desire to create a simulation log file containing some specifics?
If it is so, then you might as well use the file operations features of the RTL language you are using. First set it correctly by running normal simulation and later you can automate the test using VUnit.
Aaron Panella
@a-panella
@dpaul24 sounds like @Gitter1510 also wants to compare the output of the analyser to the vunit testbench. In this case they will need to use the logic analyser API to produce a log file in the same format... At least that is how I interpreted the question
Gitter1510
@Gitter1510
Aaron Panella nailed it! Thats exactly what i want to do :)!
is there a planned approach for this use case?
Lars Asplund
@LarsAsplund
@Gitter1510 A testbench typically checks values and states at specific points in time to determine if the DUT operates correctly or not. What you're looking for is a trace of all intermediate values. This is something that you could sample with VUnit but I think it would be better to dump these waveforms using simulator capabilities. For example save the waveform to a VCD file and then compare that to the logic analyzer output. VUnit can still setup the simulator to save the VCD and you can use a Python post check to parse and compare VCD and logic analyzer files.
Gitter1510
@Gitter1510
@LarsAsplund Thank you! Is this described in the documentation or is there an example file ?
Carlos Alberto Ruiz Naranjo
@qarlosalberto
I want to run X parallels simulations (-p argument) but I want to add a delay between launches. Could you point me to the code where I can introduce it? I would like to do a local modification in VUnit to test it
Carlos Alberto Ruiz Naranjo
@qarlosalberto
ok, got it
Lars Asplund
@LarsAsplund
@qarlosalberto What is your use case?
Carlos Alberto Ruiz Naranjo
@qarlosalberto
I'm using the delay for xsim
before xsim I run xelab. It works fine, but xelab have a memory peak at the end. If I run N testbenches in parallel I will have N memory peaks, then Vivado crashes. So I have introduced a configurable delay between launches
vruizescribano
@vruizescribano
Hi everybody. I am using VUnit+GHDL. I am trying to display with the logging library the value of a ufixed signal. In order to do that, I use "info("Fixed Value: " & to_string(to_integer(unsigned(n1))));" where "n1<=to_ufixed(6.2,n1);" The error I got in vunit says "bound check failure at" and then vunit points at the exact line where the info() is. I have read the logging library to find more information about the types that accept but I have not seen anything related to fixed points neither float point. I am also doubting about GHDL (and me) and how it handles the fixed_pkg because when I use the signal "n1" in a comparison, vunit+ghdl says it contains a metadata ('z','x','-' etc ...). Is someone working with vunit+ghdl and the fixed_pkg or float_pkg? Thanks everybody
1 reply
nfrancque
@nfrancque
@vruizescribano The "bound check failure" is coming from ghdl, not vunit. Usually means some math operation you're doing is overflowing.
vruizescribano
@vruizescribano

@vruizescribano The "bound check failure" is coming from ghdl, not vunit. Usually means some math operation you're doing is overflowing.

You are right. It looks like I am having an issue with GHDL because even a simple std_logic_vector is giving me a metadata value. This code was run using Modelsim previously without having any issue. I had big expectation with GHDL but Modelsim makes things easier. I will give a second try to GHDL if someone points out what it could be, otherwise I will switch back to Modelsim after Xmas time. Thanks!