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  • Apr 07 17:29

    kobalicek on aarch64

    Fixed cmp/cmn instructions with… (compare)

  • Apr 03 18:38
    kobalicek commented #332
  • Mar 28 23:38

    kobalicek on aarch64

    [Squash] Fixed LDR/STR family i… (compare)

  • Mar 27 10:06

    kobalicek on aarch64

    [Squash] Condition code fix (compare)

  • Mar 27 10:05

    kobalicek on aarch64

    [Squash] Condition code fix (compare)

  • Mar 26 18:00
    wky9710 commented #332
  • Mar 26 18:00
    wky9710 closed #332
  • Mar 26 09:27
    kobalicek commented #332
  • Mar 26 09:18
    kobalicek closed #329
  • Mar 26 09:18
    kobalicek commented #329
  • Mar 26 09:17
    kobalicek closed #331
  • Mar 26 09:17
    kobalicek commented #331
  • Mar 25 18:16
    wky9710 opened #332
  • Mar 22 09:41
    kobalicek commented #331
  • Mar 22 09:30
    bjorng opened #331
  • Mar 21 19:48

    kobalicek on aarch64

    Added initial AArch64 support (compare)

  • Mar 21 15:37

    kobalicek on aarch64

    Added initial AArch64 support (compare)

  • Mar 21 13:43

    kobalicek on aarch64

    Added initial AArch64 support (compare)

  • Mar 21 13:42

    kobalicek on master

    [ABI] Build improvements - repl… (compare)

  • Mar 21 12:50

    kobalicek on build_improvements

    [ABI] Build improvements - repl… (compare)

muiloo1998
@muiloo1998
maybe it depends on the group of ARM processors
Petr Kobalicek
@kobalicek
Can you be a bit more specific? According to the manual it's not encodable with LDR
so I'm really wondering which opcode you tested
muiloo1998
@muiloo1998
image.png
Petr Kobalicek
@kobalicek
I'm still pretty new to aarch64, so maybe there is something I don't know :)
muiloo1998
@muiloo1998
me too.
Petr Kobalicek
@kobalicek
but that's not AArch64, it's ARM and Thumb
muiloo1998
@muiloo1998
Petr Kobalicek
@kobalicek
Well it has like 8000 pages
Can you just provide me the relevant info?
muiloo1998
@muiloo1998
image.png
"• Base plus a scaled 12-bit unsigned immediate offset or base plus an unscaled 9-bit signed immediate offset."
Petr Kobalicek
@kobalicek
Just to finalize this - according to AArch64 Manual LDR should use LDUR in case of signed or other immediate that is not encodable with LDR
I will fix this
of course this related to more instructions, like STR as well
Petr Kobalicek
@kobalicek
@muiloo1998 I have pushed a fix, let me know whether it fixes it
865
@ichi865_twitter

Hi @kobalicek
Could you give further hints on how i can solve that issue with asmjit?
asmjit/asmjit#201

After I added the bytecode to the emitter using embed(data, size), I indicated the base address.
But now how do I relocate the bytecode to an another base address so that relative calls and jumps are converted relative to the new base address.

Petr Kobalicek
@kobalicek
What do you mean by bytecode?
If you embed data with embed, asmjit has no knowledge about such data - no relocations, nothing, it's just a binary blob it appends to the current code buffer
865
@ichi865_twitter
@kobalicek I mean a sequence of bytes of some original function that has many jumps and calls. I copied the function to buffer, but it'll not be possible to call, since addresses lead to the wrong place.
then could you tell what can I do next with that blob in order to achieve the result I want?
Petr Kobalicek
@kobalicek
I don't know, maybe use some disassembler like zydis and reassemble it, but that is not something I would want to do. Or, if you control generating of that blob, add some metadata that you can use to properly relocate it
865
@ichi865_twitter
thanks, i'll try your 1st suggestion to start with.
but why do you think this is a not good way?
865
@ichi865_twitter

hi again @kobalicek
is it possible to skip some operands during parsing?

fld st0, dword ptr ds:[eax]

like skiping st0, so that there is no error

Petr Kobalicek
@kobalicek

but why do you think this is a not good way?

I think that if you generate the blob, you should provide the information to properly use it, guessing afterwards doesn't seem like the best idea

Well I don't know - the X87 instructions follow Intel X86 Arch Manual, so they match the manual. But I would also liked more if they were explicit
Maybe I would do another iteration to match LLVM in this case, but today I don't have time unfortunately
865
@ichi865_twitter
okay, fst/fstp also not supported
or I messed up with settings
Petr Kobalicek
@kobalicek
it's all supported
865
@ichi865_twitter
https://i.imgur.com/3Zwr15E.png
apparently I was wrong somewhere
Petr Kobalicek
@kobalicek
you can see all valid signatures here:
865
@ichi865_twitter
wau cool
J.V.
@JV81608177_twitter
Hi
Is asmjit suitable for a AOT compiler ? Or only for just in time compilation ?
Petr Kobalicek
@kobalicek
both, but with AOT you have to be extremely careful about relocations
in addition, asmjit doesn't produce binaries, like .so objects, this has to be done by users, but additions are welcome :)
John Högberg
@jhogberg
I think I've found a bug in the encoding of CMP Reg, Imm on ARM, the check to see if the immediate can be shifted seems inverted
        if (immValue > 0xFFFu) {
          if ((immValue & (0xFFFu << 12)) != 0)
Shouldn't it be ~(0xFFFul << 12)?
(I noticed it after not being able to encode cmp x0, 65536 which ought to be possible if I'm reading the docs right)
Petr Kobalicek
@kobalicek
I will check it out
Petr Kobalicek
@kobalicek
you are right, thanks, I will fix that
John Högberg
@jhogberg
Sweet, thanks :)
Petr Kobalicek
@kobalicek
@jhogberg Should be fixed, thanks!
Patrick Mackinlay
@pmackinlay
Hi @kobalicek, it's been a while but I'm back to working on my own jit in MAME. I'm having trouble understanding why an instruction is failing with an invalid address error.
The code is a.call(ptr(l, rax, 3, 8)), where l is a label.
I want call qword ptr[(l+8) + rax*8] to be emitted
Patrick Mackinlay
@pmackinlay
Aha, I see my error - rip-relative addressing can only use rip + offset; back to the books.
Petr Kobalicek
@kobalicek
Actually it would work in 32-bit mode - the label would be translated to absolute address, but in 64-bit mode this doesn't work