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    black-parrot
    @black-parrot
    Welcome to the BlackParrot RTL discussion room!
    sebastien-riou
    @sebastien-riou
    Hi, the main README says "Currently, the core supports RV64IMAFD, with C support on the way!". Any idea about how far we are from that ?
    Dan Petrisko
    @dpetrisko
    Best estimate: late this summer. The actual design is fairly straightforward, but there are some performance analyses and software surveying that we want to do first. Out of curiosity, what is your use case?
    sebastien-riou
    @sebastien-riou
    Thanks for the answer. I am looking for a RISC-V 64 with at least M and C extension. C extension is useful to reduce cache miss and overall code size (we are targeting embedded systems, so memory is expensive)
    I did not manage to run most test suits, I think the current README (simple and Full) are not really in line with current state of the repo. If you know a tag or specific commit in which the guides are exactly working, that would be helpful. (so I guess it would need to have all dependencies with pin-downed revision numbers, things get old fast these days...)
    Dan Petrisko
    @dpetrisko

    Thanks for the answer. I am looking for a RISC-V 64 with at least M and C extension. C extension is useful to reduce cache miss and overall code size (we are targeting embedded systems, so memory is expensive)

    Ah, I see. Generally, we've focused on systems where having a large 32 kB I$ is sufficient to manage miss rate. But that doesn't help with code size, certainly.

    I did not manage to run most test suits, I think the current README (simple and Full) are not really in line with current state of the repo. If you know a tag or specific commit in which the guides are exactly working, that would be helpful. (so I guess it would need to have all dependencies with pin-downed revision numbers, things get old fast these days...)

    What specifically is not working? What OS? We do pin down most unstable dependencies through submodules.

    Anonymous
    @AdityaCyberSafe
    Hi
    Kylee Krzanich
    @krsandwich
    hi, is there a way to run synthesis without vivado? or just any way to extract useful timing/flop info?
    Dan Petrisko
    @dpetrisko
    It’s non-trivial to get BP through yosys due to poor SystemVerilog compatibility and hardened sram support
    Kylee Krzanich
    @krsandwich
    thanks we were able to get a vivado license! also, a couple of questions for the paging.c test:
    1. Why does the test try to create 2-megabyte pages? I don’t see any reference to these in the TLB
    2. Does the paging.c test work? It is crashing for us due to an illegal instruction at EPC 0x0000000000000540.
    Dan Petrisko
    @dpetrisko
    Good question, the TLB does not have 2MB page support. The behavior per spec is to cache a 4kB entry instead, so the test is verifying that works
    Please raise an issue if the test isn’t working for you. It’s definitely intended to pass
    Kylee Krzanich
    @krsandwich
    thanks! i will try to run the TOT to see if my changes are breaking it
    Kylee Krzanich
    @krsandwich
    hi I'm seeing this error in Vivado when I try to synthesize: ERROR: [Synth 8-27] assignment pattern with no assignment context not supported It seems to be having trouble with the line declare_bp_proc_params(bp_params_p). Have you guys seen this before? I'm not sure if vivado has issues with other declare statements in other files?
    taylor-bsg
    @taylor-bsg:matrix.org
    [m]
    Prefetching this info for Dan — which version of Vivado
    Kylee Krzanich
    @krsandwich
    oh good question. Vivado 2017.1
    taylor-bsg
    @taylor-bsg:matrix.org
    [m]
    I think 2020.1 would be a good version to standardize on
    Kylee Krzanich
    @krsandwich
    I don't think Stanford has a license for the newer version. is Black Parrot not synthesizable on the older versions?
    Dan Petrisko
    @dpetrisko
    Hi, the oldest vivado we use is 2019.X, so haven’t checked that specific version.
    taylor-bsg
    @taylor-bsg:matrix.org
    [m]
    Hi Kylee, the newer version of the tool is available for free, and some of the FPGAs are also supported for free, for example the Zynq 7020.
    Dan Petrisko
    @dpetrisko
    As a workaround, you could try changing this line: https://github.com/black-parrot/black-parrot/blob/dd2d8453a49b0f069e96f175afe97968dac205e1/bp_common/src/include/bp_common_aviary_defines.svh#L11 to simply assigning localparam bp_proc_param_s proc_param_lp = <the param struct you want>
    Dan Petrisko
    @dpetrisko
    As Prof Taylor says, I’d recommend bugging IT to upgrade the installed vivado version. There may be more issues that come up. We test with Verilator, Synopsys tools, open-source tools, and vivado but only recent versions of all