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Christopher Felton
@cfelton
I am going to setup a gsoc project through FOSSi to work on the filters and test pyfda integration
@chipmuenk can you be the backup mentor?
@chipmuenk also, ORConf is in your neck of the woods this year, fall 2018. Would you be interested in giving a co-talk?
Christopher Felton
@cfelton
"neck of the woods" is relative
Christian Münker
@chipmuenk
@cfelton, that sounds wonderful, of course I'll be the backup mentor! ORConf sounds very interesting as well, I'm not sure though whether I'll find the time. I'll decide that in the next two weeks.
Christopher Felton
@cfelton
@chipmuenk ORConf isn't until the fall, we can keep it on our radar and if it doesn't work out, no biggy
we (myhdl folks) have been trying to coordinate a time and place to meet, a conf. on ORConf makes the most sense
EU seems to be the most likely area to meet
Christian Münker
@chipmuenk
@cfelton This would be a great opportunity to meet you and some other people from the myhdl community in RL. Most likely I would have to pay for this myself, but flights are reasonable, AirBnB is cheap and I would like to visit Gdansk. Unfortunately, we may have a family meeting on the weekend of ORConf but that should be sorted out in the near future. Shall we try to do a Skype / Hangout video conference re GSOC?
Christopher Felton
@cfelton
@chipmuenk sure we can talk via vidconf (have to untape/uncover all my cameras :) ), what times work for you? I am usually up early, I am in UTC-6 (at least for a couple more weeks)
Christian Münker
@chipmuenk
@cfelton Yeah, I have to reconnect my webcam as well ;-) I am in CET (UTC+1), so it's 7 h later here. Today and for the next 2 days I'm working from home (except from some short intervals) , so you can pick a time. Is Hangouts ok? I just noticed I don't have Skype installed anymore.
Christopher Felton
@cfelton
@chipmuenk hangouts is fine, lets plan 0600 my time wed (1300 your time), I have to head into work now.
I will write up a short description and send it to you before
the projects will be under the FOSSi gsoc, https://fossi-foundation.org/gsoc18-ideas.html
Christian Münker
@chipmuenk
@cfelton 13:00 my time sounds good. I'll send you my hangouts data via PM.
Christian Münker
@chipmuenk
@cfelton and Sriyash (only just added): I've uploaded a new release to Anaconda cloud and to PyPI which fixes some minor bugs and (important for us) has a revamped interface to myhdl:
Christian Münker
@chipmuenk
  • The HDL tab only shows when myhdl is installed on the system with at least version 0.10
  • The hdl_specs.py file now dynamically loads filter design files (currently only hdl_df1.py and hdl_df2.py each with its own UI, an image of the filter topology and the myhdl description of filter topology. The filter design files are more or less demo files to test error catching and the interaction between myhdl and pyfda without proper functionality.
  • The hdl_specs.py file triggers HDL conversion (works for a biquad, although none of the UI information is used for conversion). Fixpoint simulation still throws an error (now "Simulation failed: Inappriopriate argument type:" )
    Perhaps both of you could take a look (also at the error) and then we could start the discussion.
Christian Münker
@chipmuenk
grafik.png
... installing / updating is easy: conda install / update -c Chipmuenk pyfda or
pip install pyfda -U .
Christopher Felton
@cfelton
I pulled the latest from github (I thought I did) and I don't see the stuff you added - will investigate
Christopher Felton
@cfelton
that was odd, I had to pull twice to get all the updates?
image.png
@sriyash25, an exercise that could be useful, is for you to write down (document) all the arguments/parameters that should be passed to the hardware filter blocks from pyfda and what should be passed back.
Sriyash Caculo
@sriyash25
@cfelton , Yes, will get to it.
Christian Münker
@chipmuenk
I've no idea what was wrong with GitHub ... the latest released version is under "master", the latest (more or less) working version is in the "develop" branch. The graphics is missing intentionally to check try ... except. Do you also have problems with resizing the graphics (slow / jumpy)? I've also just noticed that filter loading / saving is more or less defunct due to several bugs. Working on that.
Sriyash Caculo
@sriyash25
As for the parameters that will be needed to be passed to the hardware filter blocks we will need: Filter coefficients (b,a for IIR and b for FIR) and ‘word_format'. I noticed in the current implementation ‘sos' is also being passed to myhdl, it is obviously not necessary but in any case, will we need that too? Return parameters could be success / fail for synthesis, and an array ‘y’ for simulation. Let me know if I have missed something.
Also, I suppose the implementation can be done only for a particular order of filter? For example, second order systolic FIR. How will we go about implementation for different orders of filters?
Christian Münker
@chipmuenk
I agree with the coefficients and the word format (WI, WF) for different parts of the filter topology (e.g. input, output, accumulator). I'm building a dict that contains these informations, additionally I'm providing data on how to requantize data (saturation or wrapping, truncation or fix() etc).
For IIR filters we will need coefficients in SOS format to obtain stable filters. One of the main advantages of using myHDL over a simple templating approach is that we have the power of python at hand: The fixpoint implementations should be intelligent enough to create topologies depending on the filter order. @cfelton : You have developed myHDL descriptions like this, haven't you?
Return parameters: sounds good to me.
Christian Münker
@chipmuenk
Sriyash,
waiting for a month for a board wouldn't be a problem IMHO as you have to start with interface definition and high level coding anyway.
You should use what works best for you,
but I think that uploading and running a bit file to an FPGA is optional, synthesizing / simulating HDL code in Vivado is the important part. Verifying correct performance
Christopher Felton
@cfelton
I agree with the statements
Christian Münker
@chipmuenk
on an FPGA board is a difficult task.
What do you think about using Trello for
Sriyash Caculo
@sriyash25
I will take this up again with my prof. If it doesn't work out, using the existing boards as a last resort should be okay?
Christopher Felton
@cfelton
i am not familiar with Trello - can't say one way or the other.
@sriyash25 yes that would be fine
Christian Münker
@chipmuenk
@sriyash25 : for me too
Christopher Felton
@cfelton
@sriyash25 note you should create a blog in the next week or two, simply stating who you are and what you are doing, etc.
then you can post the blog to LibreCores as your introduction
if you want you can post your blogs here: https://www.dsprelated.com/
I would prefer you post your blogs at dsprelated but I am ok with others as well.
Sriyash Caculo
@sriyash25
@cfelton Yes, the first post could just be a summery of the project and a bit of introduction?
Christopher Felton
@cfelton
yes
Sriyash Caculo
@sriyash25
Great, will stick to dsprelated
Christopher Felton
@cfelton
I would keep the post simple, it can be hard, but state only the 100% items
possibly the first two items for the project and leave the third unstated for now
Sriyash Caculo
@sriyash25
yes, got it
Christopher Felton
@cfelton
leave the external expectations low
Sriyash Caculo
@sriyash25
also, slightly unrelated topic, needed confirmation on filter order for implementation? The previous attempt, if I may call it so, was 2nd order filter implementation only. How do I go about implementing different orders to interface with pyfda?
Christopher Felton
@cfelton
most practical implementations are cascaded 2nd order filters (second order sections)