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  • Dec 03 08:28

    chipmuenk on develop

    replace stop by play icon, func… Clean up logging statements Sig… (compare)

  • Dec 02 17:50

    chipmuenk on develop

    increase margins for some butto… streamline code a little Signed… (compare)

  • Dec 01 08:41

    chipmuenk on master

    allow writing "j" for imaginary… Merge branch 'develop' of https… fix some formatting issues Sign… and 23 more (compare)

  • Dec 01 08:41

    chipmuenk on develop

    replace time.perf_counter_ns() … rename update_fx_ui() -> update… update some comments Signed-off… and 1 more (compare)

  • Nov 30 21:27

    chipmuenk on develop

    Change button state "failed" to… make behaviour of run / autorun… fix formatting errors Signed-of… and 10 more (compare)

  • Nov 28 17:43

    chipmuenk on develop

    fix visibility of E_x button an… (compare)

  • Nov 27 14:23

    chipmuenk on develop

    update docstring (compare)

  • Nov 26 08:20

    chipmuenk on develop

    Change icon of run button to "s… Fix auto selection of frame len… Add stop icon Signed-off-by: Ch… (compare)

  • Nov 25 16:50

    chipmuenk on develop

    allow writing "j" for imaginary… Merge branch 'develop' of https… fix some formatting issues Sign… and 1 more (compare)

  • Nov 25 08:43

    chipmuenk on master

    formatting updates Signed-off-b… Operate fixpoint filters with Q… clean up code Signed-off-by: Ch… and 31 more (compare)

  • Nov 25 08:43

    chipmuenk on develop

    Reduce width of progress bar Si… (compare)

  • Nov 24 11:33

    chipmuenk on develop

    change initial settings Signed-… (compare)

  • Nov 22 16:24

    chipmuenk on develop

    reduce logging noise, update co… (compare)

  • Nov 22 15:11

    chipmuenk on develop

    process signals from local fx w… emit {'fx_sim': 'specs_changed'… (compare)

  • Nov 19 13:35

    chipmuenk on develop

    fix wrong name in signal, preve… Fix HDL creation widget becomin… Update docstrings Signed-off-by… and 4 more (compare)

  • Nov 18 12:25

    chipmuenk on develop

    only print first dict_sig k,v; … Only emit a signal when widgets… reformatting Signed-off-by: Chr… and 5 more (compare)

  • Nov 18 04:32
    chipmuenk commented #205
  • Nov 18 01:49
    CybEng opened #205
  • Nov 17 17:58

    chipmuenk on develop

    improve logger formatting Signe… Only log first item of dict_sig… (compare)

  • Nov 17 07:39

    chipmuenk on develop

    update docstrings Signed-off-by… rename to_verilog to to_hdl Sig… try remembering results from la… and 2 more (compare)

Christian Münker
@chipmuenk
... installing / updating is easy: conda install / update -c Chipmuenk pyfda or
pip install pyfda -U .
Christopher Felton
@cfelton
I pulled the latest from github (I thought I did) and I don't see the stuff you added - will investigate
Christopher Felton
@cfelton
that was odd, I had to pull twice to get all the updates?
image.png
@sriyash25, an exercise that could be useful, is for you to write down (document) all the arguments/parameters that should be passed to the hardware filter blocks from pyfda and what should be passed back.
Sriyash Caculo
@sriyash25
@cfelton , Yes, will get to it.
Christian Münker
@chipmuenk
I've no idea what was wrong with GitHub ... the latest released version is under "master", the latest (more or less) working version is in the "develop" branch. The graphics is missing intentionally to check try ... except. Do you also have problems with resizing the graphics (slow / jumpy)? I've also just noticed that filter loading / saving is more or less defunct due to several bugs. Working on that.
Sriyash Caculo
@sriyash25
As for the parameters that will be needed to be passed to the hardware filter blocks we will need: Filter coefficients (b,a for IIR and b for FIR) and ‘word_format'. I noticed in the current implementation ‘sos' is also being passed to myhdl, it is obviously not necessary but in any case, will we need that too? Return parameters could be success / fail for synthesis, and an array ‘y’ for simulation. Let me know if I have missed something.
Also, I suppose the implementation can be done only for a particular order of filter? For example, second order systolic FIR. How will we go about implementation for different orders of filters?
Christian Münker
@chipmuenk
I agree with the coefficients and the word format (WI, WF) for different parts of the filter topology (e.g. input, output, accumulator). I'm building a dict that contains these informations, additionally I'm providing data on how to requantize data (saturation or wrapping, truncation or fix() etc).
For IIR filters we will need coefficients in SOS format to obtain stable filters. One of the main advantages of using myHDL over a simple templating approach is that we have the power of python at hand: The fixpoint implementations should be intelligent enough to create topologies depending on the filter order. @cfelton : You have developed myHDL descriptions like this, haven't you?
Return parameters: sounds good to me.
Christian Münker
@chipmuenk
Sriyash,
waiting for a month for a board wouldn't be a problem IMHO as you have to start with interface definition and high level coding anyway.
You should use what works best for you,
but I think that uploading and running a bit file to an FPGA is optional, synthesizing / simulating HDL code in Vivado is the important part. Verifying correct performance
Christopher Felton
@cfelton
I agree with the statements
Christian Münker
@chipmuenk
on an FPGA board is a difficult task.
What do you think about using Trello for
Sriyash Caculo
@sriyash25
I will take this up again with my prof. If it doesn't work out, using the existing boards as a last resort should be okay?
Christopher Felton
@cfelton
i am not familiar with Trello - can't say one way or the other.
@sriyash25 yes that would be fine
Christian Münker
@chipmuenk
@sriyash25 : for me too
Christopher Felton
@cfelton
@sriyash25 note you should create a blog in the next week or two, simply stating who you are and what you are doing, etc.
then you can post the blog to LibreCores as your introduction
if you want you can post your blogs here: https://www.dsprelated.com/
I would prefer you post your blogs at dsprelated but I am ok with others as well.
Sriyash Caculo
@sriyash25
@cfelton Yes, the first post could just be a summery of the project and a bit of introduction?
Christopher Felton
@cfelton
yes
Sriyash Caculo
@sriyash25
Great, will stick to dsprelated
Christopher Felton
@cfelton
I would keep the post simple, it can be hard, but state only the 100% items
possibly the first two items for the project and leave the third unstated for now
Sriyash Caculo
@sriyash25
yes, got it
Christopher Felton
@cfelton
leave the external expectations low
Sriyash Caculo
@sriyash25
also, slightly unrelated topic, needed confirmation on filter order for implementation? The previous attempt, if I may call it so, was 2nd order filter implementation only. How do I go about implementing different orders to interface with pyfda?
Christopher Felton
@cfelton
most practical implementations are cascaded 2nd order filters (second order sections)
Sriyash Caculo
@sriyash25
@chipmuenk I'm not familiar with trello, don't mind trying.
@cfelton right, I'll stick to 2nd order in that case
Christopher Felton
@cfelton
we should be able to make it general enough for any order (but there will probably be intermediate value overflows or very large word widths)
Christian Münker
@chipmuenk
I suggest starting with a simple direct form topology
to gain experience with filters with parametrized order in myhdl, never mind that practical iir filters are usually not implemented that way.
Sriyash Caculo
@sriyash25
@chipmuenk Should I try interfacing a simple moving average filter?
Sriyash Caculo
@sriyash25
The HDL generation seems to be working although I haven't actually checked if the results are accurate.
Christian Münker
@chipmuenk
Yes, you could start with simple FIR-filter if that's what you mean - some books refer to FIR filters as "moving average" or "MA". In pyfda, the term moving average filter is used more strictly for a filter where all coefficients are 1. This should be implemented accordingly with a simple accumulator in HDL.
For a start, you could restrict your filter to a fixed order of say 10, then we should discuss with @cfelton how to parametrize the order.
Christopher Felton
@cfelton
I think there is a general design topic that needs to be determined - should the digital circuit blocks be encapsulated in an object (the original example) or a block with a parameter object.
for the first examples might seem overkill, having a few arguments would suffice
in the long term the filter-blocks should receive design parameters from pyfda and have the ability to send simulation data, etc. back.
Christian Münker
@chipmuenk
I really haven't worked with myhdl blocks so I don't know their limits. The API seems nice though. Wouldn't it be worth a try to design a simple implemementation (DF FIR filter ;-) ...) using a myhdl block to gain a better understanding? The time wouldn't be lost as we have to specify + improve the interface between myhdl and pyfda anyway.
BTW: I'm currently finishing a new pyfda release with some changes to the HDL generation part. Hopefully you haven't started to dig into that part too much.
Christopher Felton
@cfelton
the block decorator doesn't provide much to the user, it is really an internal myhdl thing to simplify some things, it is nice because in explicitly labels functions/methods that are myhdl.blocks
I think the best method, is to implement the digital hardware descriptions like the example I posted, but then to create a class that will encapsulate the parameters, control, and status of the filter creation
the API to pyfda will be provided by these objects and they can be coded here https://github.com/cfelton/filter-blocks/tree/master/filter_blocks/fda
Christopher Felton
@cfelton
the link shows the block usage, not the FIR implementation