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  • Dec 02 17:07

    chipmuenk on develop

    prevent crash when cancelling f… Clean up code Signed-off-by: Ch… (compare)

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    chipmuenk on develop

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    chipmuenk on develop

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    chipmuenk on develop

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    chipmuenk on develop

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    chipmuenk on develop

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    chipmuenk on develop

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  • Oct 27 16:08

    chipmuenk on develop

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  • Oct 26 06:34
    chipmuenk commented #230
Christopher Felton
@cfelton
we should be able to make it general enough for any order (but there will probably be intermediate value overflows or very large word widths)
Christian Münker
@chipmuenk
I suggest starting with a simple direct form topology
to gain experience with filters with parametrized order in myhdl, never mind that practical iir filters are usually not implemented that way.
Sriyash Caculo
@sriyash25
@chipmuenk Should I try interfacing a simple moving average filter?
Sriyash Caculo
@sriyash25
The HDL generation seems to be working although I haven't actually checked if the results are accurate.
Christian Münker
@chipmuenk
Yes, you could start with simple FIR-filter if that's what you mean - some books refer to FIR filters as "moving average" or "MA". In pyfda, the term moving average filter is used more strictly for a filter where all coefficients are 1. This should be implemented accordingly with a simple accumulator in HDL.
For a start, you could restrict your filter to a fixed order of say 10, then we should discuss with @cfelton how to parametrize the order.
Christopher Felton
@cfelton
I think there is a general design topic that needs to be determined - should the digital circuit blocks be encapsulated in an object (the original example) or a block with a parameter object.
for the first examples might seem overkill, having a few arguments would suffice
in the long term the filter-blocks should receive design parameters from pyfda and have the ability to send simulation data, etc. back.
Christian Münker
@chipmuenk
I really haven't worked with myhdl blocks so I don't know their limits. The API seems nice though. Wouldn't it be worth a try to design a simple implemementation (DF FIR filter ;-) ...) using a myhdl block to gain a better understanding? The time wouldn't be lost as we have to specify + improve the interface between myhdl and pyfda anyway.
BTW: I'm currently finishing a new pyfda release with some changes to the HDL generation part. Hopefully you haven't started to dig into that part too much.
Christopher Felton
@cfelton
the block decorator doesn't provide much to the user, it is really an internal myhdl thing to simplify some things, it is nice because in explicitly labels functions/methods that are myhdl.blocks
I think the best method, is to implement the digital hardware descriptions like the example I posted, but then to create a class that will encapsulate the parameters, control, and status of the filter creation
the API to pyfda will be provided by these objects and they can be coded here https://github.com/cfelton/filter-blocks/tree/master/filter_blocks/fda
Christopher Felton
@cfelton
the link shows the block usage, not the FIR implementation
Christian Münker
@chipmuenk
Only had the time for a quick look: Looks clear & good, I would only suggest handling the float -> integer conversion of coefficients in pyfda so that the user can make a first estimation whether coefficient quantizations has an disastrous effect. It would also be nice if quantization parameters (e.g. accumulator wordlength and requantization method like floor, fix etc) could be controlled via the ui.
Currently, I'm developing in the branch 'hdl_interface', I've renamed the directory with the fixpoint implementations and some files and I'm in the process of redesigning where and how pyfda looks for user files at startup. Perhaps you can take a look before I merge some time next week.
Christopher Felton
@cfelton
@sriyash25 @chipmuenk we started a discussion, how to pass all the parameters to the filter-blocks
one idea is to have a class that can be used to set all the parameters
Christopher Felton
@cfelton

from ..fir import filter_fir_df

class FIRFilter(HardwareFilter):
    def __init__(self, b):
        self.filter_type = 'direct_form'
        self.n_cascades = 0

    def set_cascade(self, n_cascades):
        self.n_cascades = n_cascades

    @hdl.block
    def filter_block(self, glbl, sigin, sigout):
        # this elaboration code will select the different structure and implementations
        if self.filter_type == 'direct_form':
            if self.direct_form_type == 1:
                # all filters will need the same interface ports, this should be do able
                dfilter = filter_fir_df

            if self.n_cascades > 0:
                filter_insts = [None for _ in range(self.n_cascades)]
                for ii in range(self.n_cascades):
                    filter_insts[ii] = dfilter(
                        glbl, sigin[ii], sigout[ii]
                    )
            else:
                filter_inst = dfilter(...)
there are a lot of details missing
this api will take some experimentation to figure out
these objects would live in filter_blocks/fda/fir.py, filter_blocks/fda/iir.py etc.
Sriyash Caculo
@sriyash25
Okay, I think we can start with DF1 FIR and come to cascades later (as suggester by Christian). I will attempt to set parameters through this class and see how it goes.
Christian Münker
@chipmuenk
@cfelton I agree that organizing filters in a class or in several classes is a good approach to bundle all the functionality we need:
  • setting (and maybe getting) parameters like internal and external word formats or coefficients. I suggest a setter method with **kwargs
  • fixpoint simulation stuff
  • HDL synthesis stuff
  • maybe information on internal quanization noise on an algorithmic / behavioural level etc.
Christian Münker
@chipmuenk
I'm not sure though whether it is easier to write one class per filter implementation (given that fixpoint implementations can be very different in e.g. their parameters and simulation setup) or to create a large class.
Sriyash Caculo
@sriyash25
@chipmuenk I was under the impression that we would be creating only two classes for now, one for fir and one for iir filters. Although, even these two can be bundled into one
Christopher Felton
@cfelton
you want a hierarchy, and only create a new class based on the subclasses if one is needed
Christian Münker
@chipmuenk
I think we have reached a point where it would be best to whip up an example that we can use as a base for discussion. In pyfda, I can now easily write a dict with integer coefficients and word lengths and trigger HDL conversion.
My next step would be to think about a way for importing data from fixpoint simulation.
Christian Münker
@chipmuenk
To give some inspiration to our discussion tomorrow, here are a some screenshots from Mathworks fdatool with fixpoint toolbox:
fdatool_quant1
fdatool_quant2.png
fdatool_quant3.png
fdatool_quant3b.png
fdatool_quant3d.png
Christian Münker
@chipmuenk
And this the UI of the current pyfda development:
pyfdax_fixpoint.png
Christian Münker
@chipmuenk

I suggest the following discussion topics for tomorrow:

  • State / progress of the project

  • Import mechanism pyfda <-> myhdl

  • File / directory structure: How do we organize the myhdl and UI descriptions
  • Who you're gonna call: Communication between myhdl and pyfda
  • Interfaces for fixpoint simulations: input data, number of points, output format ...

  • Fixpoint filter implementations: next steps

  • Integration into the myhdl ecosystem
Sriyash Caculo
@sriyash25
A brief summery of the discussion
  • Import mechanism pyfda <-> myhdl
    We will have multiple classes for different filter implementations inheriting from whichever class appropriate. Base class FilterHardware.
    Pyfda will import class as follows: from filter_blocks.fda import FIRFilter
    parameters can be set and simulation run as follows:
    hdlfilter = FIRFilter()
    hdlfilter.set_coefficients(b)
    hdlfilter.run_sim()
    y = hdlfilter.get_response()
  • #55 (issue) demo of fixpoint simulation to be carried out for the fir_df1 filter. Output would be returned as a numpy array.
  • Rounding modes support (ceiling, floor etc.) has to be provided in filter-blocks repo
  • further discussion on limiting wordlengths based on FPGA family for optimal use of resources, providing warnings if wordlength is not ideal.
I may have missed some points
Christopher Felton
@cfelton
@sriyash25 good summary, that covers it.
Christopher Felton
@cfelton
adding the import to the code example
from filter_blocks.fda import FIRFilter

hdlfilter = FIRFilter()            # Standard DF1 filter 
hdlfilter.set_coefficients(b)      # Coefficients for the filter
hdlfilter.set_stimulation(x)       # Set the simulation input
hdlfilter.run_sim()                # Run the simulation
y = hdlfilter.get_response()       # Get the response from the simulation
note, on the pyfda side, the simulation should probably run in a separate thread or subprocess
Sriyash Caculo
@sriyash25
@chipmuenk , @cfelton So far, I was using a tool called gtkwave to view the waveform and verify outputs of simulation. I had written small test benches to pass parameters to the filter block and trace the signal. The test bench would output a .vcd file which can be viewed using the tool mentioned. here is the test bench for fir_df1: https://github.com/cfelton/filter-blocks/blob/master/tests/test_fir/test_df1.py . Of course, this code will not be necessary once the parameters are being passed from PyFDA, but I suppose for now , we still want output the .vcd file to verify simulation results?
Christopher Felton
@cfelton
this is a good way to start and debug
in the filter_blocks package we want to automated tests for everything, 100% tested
the tests will need to be self checking.