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  • Dec 02 17:07

    chipmuenk on develop

    prevent crash when cancelling f… Clean up code Signed-off-by: Ch… (compare)

  • Dec 01 08:14

    chipmuenk on develop

    use fixed sniffer size for the … (compare)

  • Nov 30 16:59

    chipmuenk on develop

    add "w" and "wb" option to sele… Try slicing multi-channel data … update docstrings, clean up com… and 9 more (compare)

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    chipmuenk on develop

    Add widgets for selection of da… make widget for data selection … (compare)

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    chipmuenk on develop

    function attributes only become… Button has to be non-checkable … Only reset file status when no … and 12 more (compare)

  • Nov 14 19:48

    chipmuenk on develop

    enable debug message Signed-off… Merge branch 'develop' of https… Merge branch 'develop' of https… and 1 more (compare)

  • Nov 14 19:17

    chipmuenk on develop

    Limit length of filename to 45 … Fix calculation and display of … start gathering informations ab… and 8 more (compare)

  • Nov 07 19:05

    chipmuenk on develop

    Clean up UI Signed-off-by: Chri… (compare)

  • Nov 04 18:42

    chipmuenk on develop

    simplify loading of frequency r… simplify loading of frequency s… control subwidgets visibility, … and 10 more (compare)

  • Nov 02 19:49

    chipmuenk on develop

    return -1 when an error occurs … Don't emit a signal here, it is… (compare)

  • Oct 29 17:47

    chipmuenk on develop

    comment out recipe, should be p… (compare)

  • Oct 29 16:47

    chipmuenk on develop

    fix another syntax error Signed… (compare)

  • Oct 29 16:42

    chipmuenk on develop

    fix some more syntax errors Sig… (compare)

  • Oct 29 16:18

    chipmuenk on develop

    remove pipe Signed-off-by: Chri… (compare)

  • Oct 29 15:53

    chipmuenk on develop

    play around with workflow for A… Fix initialization error that c… (compare)

  • Oct 29 14:24

    chipmuenk on develop

    Improve tool tip Signed-off-by:… (compare)

  • Oct 27 16:08

    chipmuenk on develop

    define new function for reading… add more ui elements Signed-off… create new attribute self.data … and 7 more (compare)

  • Oct 26 07:37

    chipmuenk on develop

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  • Oct 26 07:11

    chipmuenk on main

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  • Oct 26 06:34
    chipmuenk commented #230
Sriyash Caculo
@sriyash25
@chipmuenk I was under the impression that we would be creating only two classes for now, one for fir and one for iir filters. Although, even these two can be bundled into one
Christopher Felton
@cfelton
you want a hierarchy, and only create a new class based on the subclasses if one is needed
Christian Münker
@chipmuenk
I think we have reached a point where it would be best to whip up an example that we can use as a base for discussion. In pyfda, I can now easily write a dict with integer coefficients and word lengths and trigger HDL conversion.
My next step would be to think about a way for importing data from fixpoint simulation.
Christian Münker
@chipmuenk
To give some inspiration to our discussion tomorrow, here are a some screenshots from Mathworks fdatool with fixpoint toolbox:
fdatool_quant1
fdatool_quant2.png
fdatool_quant3.png
fdatool_quant3b.png
fdatool_quant3d.png
Christian Münker
@chipmuenk
And this the UI of the current pyfda development:
pyfdax_fixpoint.png
Christian Münker
@chipmuenk

I suggest the following discussion topics for tomorrow:

  • State / progress of the project

  • Import mechanism pyfda <-> myhdl

  • File / directory structure: How do we organize the myhdl and UI descriptions
  • Who you're gonna call: Communication between myhdl and pyfda
  • Interfaces for fixpoint simulations: input data, number of points, output format ...

  • Fixpoint filter implementations: next steps

  • Integration into the myhdl ecosystem
Sriyash Caculo
@sriyash25
A brief summery of the discussion
  • Import mechanism pyfda <-> myhdl
    We will have multiple classes for different filter implementations inheriting from whichever class appropriate. Base class FilterHardware.
    Pyfda will import class as follows: from filter_blocks.fda import FIRFilter
    parameters can be set and simulation run as follows:
    hdlfilter = FIRFilter()
    hdlfilter.set_coefficients(b)
    hdlfilter.run_sim()
    y = hdlfilter.get_response()
  • #55 (issue) demo of fixpoint simulation to be carried out for the fir_df1 filter. Output would be returned as a numpy array.
  • Rounding modes support (ceiling, floor etc.) has to be provided in filter-blocks repo
  • further discussion on limiting wordlengths based on FPGA family for optimal use of resources, providing warnings if wordlength is not ideal.
I may have missed some points
Christopher Felton
@cfelton
@sriyash25 good summary, that covers it.
Christopher Felton
@cfelton
adding the import to the code example
from filter_blocks.fda import FIRFilter

hdlfilter = FIRFilter()            # Standard DF1 filter 
hdlfilter.set_coefficients(b)      # Coefficients for the filter
hdlfilter.set_stimulation(x)       # Set the simulation input
hdlfilter.run_sim()                # Run the simulation
y = hdlfilter.get_response()       # Get the response from the simulation
note, on the pyfda side, the simulation should probably run in a separate thread or subprocess
Sriyash Caculo
@sriyash25
@chipmuenk , @cfelton So far, I was using a tool called gtkwave to view the waveform and verify outputs of simulation. I had written small test benches to pass parameters to the filter block and trace the signal. The test bench would output a .vcd file which can be viewed using the tool mentioned. here is the test bench for fir_df1: https://github.com/cfelton/filter-blocks/blob/master/tests/test_fir/test_df1.py . Of course, this code will not be necessary once the parameters are being passed from PyFDA, but I suppose for now , we still want output the .vcd file to verify simulation results?
Christopher Felton
@cfelton
this is a good way to start and debug
in the filter_blocks package we want to automated tests for everything, 100% tested
the tests will need to be self checking.
you could do something like an impulse input and verify the impulse out (for the fir will be the coefficients)
or you can verify the response for a subset of filters
Sriyash Caculo
@sriyash25
But how do we verify simulation results once we pass parameters using PyFDA instead of the testbench? do we still need to trace the signal and generate the .vcd file or simply pass y back to pyfda?
Christopher Felton
@cfelton
there should be an option to enable tracing
same that exists now
hdlfilter.config_sim(trace=True)
that is a debug option, generally shoudn't be needed.
Sriyash Caculo
@sriyash25
Right, got it
Christopher Felton
@cfelton
the pyfda will be able to plot the input signal and output signal, in someways it provides manual verification
Animesh Srivastava
@animeshsrivastava24
Hello, my name is Animesh Srivastava. I am a 4th Year student from NIT Hamirpur, India from Electronics and Communication Branch. I am looking forward to contribute to pyFDA. I have an experience of 2 years working with Python Language and Verilog. I am open to learn new skills and develop my prowess. I believe that my experience will help me to work on this project. Please guide me with the initial task to move on with it. Regards.
Christian Münker
@chipmuenk
Hello Animesh,
Animesh Srivastava
@animeshsrivastava24
I'm highly thankful to your reply @chipmuenk , hello.
Christian Münker
@chipmuenk
thanks for your interest in the pyfda project, @animeshsrivastava24 ! Unfortunately, I'm really busy at the moment, I haven't even managed to fully merge Sriyash's work until now. I'm afraid I won't find any time for pyfda related activities till the end of the year. I'm planning to better integrate @sriyash25 's and @cfelton 's contributions to myhdl / pyfda integration in the quiet time between Xmas and mid of January, your expertise would be highly welcome then.
Animesh Srivastava
@animeshsrivastava24
@chipmuenk I'm aiming for GSOC 2019. Sure, I'm enthusiastically looking for contributions. Meanwhile I'm devoting my time to learn more about the project and fixing initial bugs and issues mentioned.