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    develone
    @develone

    Hello

    I understand that you are working with a IcoBoard
    using a Raspberry Pi.

    I have been trying to learn fpga with the help of Chris Felton
    & Dave Vandenbout.

    develone
    @develone

    I recently updated you tools icestorm b49d2d3e78cd6, arachne_pnr
    1a4fdf96a7fd, yosys 840a6dc8932211 and iverilog 1ea8a13bf877e6e.

    I have used your tools to sucessfully program the CAT-Board &
    led digit array that I got from Dave.

    I made a time laspe video that I have at the following link.
    This was 3 hours which you can see in 43 sec.

    http://99.184.183.104/video.webm

    develone
    @develone

    I am using Chris Felton rhea and Jan's MyHDL.

    My application is the dwt of jpeg-2000.

    I programmmed the ICE40-HX8K with catboard.bin obtained
    after running the "python catboard_blinky_host.py --build"

    I see the led blink at 1 per sec.
    When you send 02de 0000 2000 ca04 0000 ff00
    over the serial port at 115200 you should see
    all the leds turn on.

    Using the catboard.v & catboard.pcf and the Lattice
    iCEcube2 which provides catboard_bitmap.bin all works as
    expected.

    develone
    @develone
    I can provide additional information build logs and timing information with you icetime.
    Scott Baker
    @scottlbaker
    I just filed a question on Stack Overflow about a programming permission problem I'm having. Piotr Esden-Tempski helped steer me in the right direction, but I have not resolved the problem yet. Can anyone here help take a look? http://stackoverflow.com/questions/36633819/iceprog-cant-find-ice-ftdi-usb-device-linux-permission-issue
    Piotr Esden-Tempski
    @esden
    you can use lsusb to see what product and vendor id your ftdi device has
    Scott Baker
    @scottlbaker
    lsusb shows idVendor=="0403" and idProduct=="6010". I tried the suggested udev/rules at http://developer.intra2net.com/mailarchive/html/libftdi/2009/msg00186.html, but iceprog is still not working for non-root users.
    Scott Baker
    @scottlbaker
    Thanks everyone, the programming permission problem that I had is now resolved. Now I have a new question: I have a design with an embedded processor that needs to boot from a block RAM structure. I know I can write the RTL to include initial RAM values but I would like a method that doesn't require a full FPGA recompilation to change the program in the block RAMs. Is there a way to modify a Lattice bitstream file to load new data for the block RAMs?
    Piotr Esden-Tempski
    @esden
    I have not done any of that, and I did not even know that this is something one would want to do.
    but I googled for the icestorm documentation and found this
    you might be able to modify the bitstream to include a different BRAM in the stream
    you could also look for the options available in IceProg utility
    maybe it provides a way of reprogramming the BRAM section on it’s own without touching the rest of the bitstream on the chip
    again not sure if that is useful at all, as I have never done such a thing
    I know @cliffordwolf was uploading the bitstream directly to the FPGA bypassing the bitstream flash completely using his tools
    that might be something you want to look into
    Scott Baker
    @scottlbaker
    Thanks for the pointer Piotr. My current iCE40 FPGA project includes an 8-bit (soft IP) microprocessor connected to a 4Kx8 RAM which is composed from 8 2Kx2 block RAMs. It would be useful to be able to load new programs (for the 8-bit micro) into the 4kx8 RAM without requiring an FPGA recompile or reroute. The proposed flow would need to a) analyze the FPGA netlist to figure out how the 8 2Kx2 block RAMs (that compose the 4Kx8 RAM) are arranged and named. b) split the Intel hex file that contains the new program (8-bit-micro) into 8 sections. c) find each of the 8 block RAM data sections in the bitstream and replace the current content of each section with the new program content. I think the icestorm project may have reverse-engineered enough info to make this proposed flow possible.
    Piotr Esden-Tempski
    @esden
    Yeah as I said, you will have to look into it yourself. All I said is only based on <5min google search. I am not sure there is an icestorm mailinglist. But maybe an issue on github would help or asking on stack overflow. Otherwise you will have to go down the rabbit hole of figuring it out yourself. :( I bet it would be useful for everyone to have this functionality. I assume this is similar to what @cliffordwolf did on the http://icoboard.org/ running the https://github.com/cliffordwolf/picorv32
    there are some tools in the raspberry pi image that are used to upload the code to the picorv32 as far as I understand
    again, you need to go down that rabbit hole yourself … I do not know enough about it to be helpful
    Scott Baker
    @scottlbaker
    Thanks Piotr. I am hoping that Clifford Wolf reads this thread and that perhaps he has already solved this. I have also filed a Lattice tech support ticket to ask if they have a solution. Several years ago I faced a similar issue with Xilinx and the iSE tool suite and I was able to create a flow to do this.
    Piotr Esden-Tempski
    @esden
    you know that Lattice has nothing to do and has no association with icestorm or Yosys and I doubt they will be willing or able to help you with that...
    Scott Baker
    @scottlbaker
    Yes, my question to Lattice did not mention icestorm or yosys.
    Marko Havu
    @mhavu
    I am taking the first steps to formally verify my SPI module. On the first round I got "smt2: ERROR: Found logic loop in module spi!", so I added write_smt2 between ghdl and prep. Now I get "base: ERROR: Unsupported cell type $adff for cell spi." Is there something I could try as the next step, or is it impossible to say without seeing the files?
    Marko Havu
    @mhavu
    BTW, why does it say cell and not module in that second error message?
    Marko Havu
    @mhavu
    Hmm... I converted the design to Verilog, and Yosys seems to be happy with it. I guess the issue is with something ghdl does.
    Marko Havu
    @mhavu
    Rubber duck debugging revealed that the VHDL file I was trying to feed to Yosys was not from the same version of the design as the Verilog file. 🤦 With the latest version everything works just fine.
    David R. Piegdon
    @dpiegdon
    hi everyone
    thanks to the developers of yosys and all the other great tools I now use regularly!
    I have a question about parameters and localparams, I hope you can help me:
    I often use a localparam to calculate the number of pins required in a module interface, e.g.: localparam pincount=$clog(max_value). this seems fine, and I can use the value pincount in the module interface: input wire [pincount-1:0] val;
    but some functions like $ceil or $sqrt render the value incalculable. if I use those localparams in the module interface, I get an error:
    ERROR: Failed to detect width for parameter \PINCOUNT!
    is this a bug, or is it wanted behaviour? is it even legal to use localparams in the interface? I think many other tools raise an error if I do that. is there a description somewhere in the documentation, which functions are valid, which are not in that context?
    David R. Piegdon
    @dpiegdon
    (switched to #yosys in freenode, as this channel here seems pretty dead)