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  • Aug 17 08:29

    bessman on main

    Fix typo in README (compare)

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Alexander Bessman
@bessman
set_state simply sets the SQ-pins either high or low.
If you're asking about this specific usage of set_state, PWMGenerator uses the firmware function sqr4. This function outputs a PWM signal on every SQ-pin, including pins which should be constant high or constant low. It is therefore necessary to reset pins which should not have PWM signals on them after calling the firmware function.
This is a workaround for some firmware bugs/limitations. In the next firmware version these should be resolved, but for now this is necessary.
nielek2
@nielek2
Figure_1.png
(images don't seem to work in threads, so this TCD1304 in a dark box)
Figure_2.png
Kartikay Sharma
@kartikaysharma01
In pslab-python, if I do wavegen.generate("SI1",2500) and then connect SI1 to CH2, on sampling using oscilloscope.capture(2,100,1) the noise values on CH1 change too. Is this the expected behavior? @bessman Can you reproduce this too?
Alexander Bessman
@bessman
Yes, there is some crosstalk between the channels.
nielek2
@nielek2
tcd1304-timing-es.png
so i ICG needs to be low before the sampling and goes low again at the end of the samling process, correct?
Alexander Bessman
@bessman
That's my understanding, yes.
NAVEEN S R
@nkpro2000sr

Regarding tests/test_spi.py:

For testing SPI transfer, I planned to connect MISO and MOSI (SDO -> SDI). Simple but, has some cons: can't test write and read independently, and can't test SMP bit of SPI config (main problem).

Then second plan, use logic analyser for MOSI and PWM generator for MISO. By this we can test write and read separately and can test SMP bit of SPI config. But testing SMP bit need precision PWM wave generation.

Like:

testSMPbit.png
My question: is it possible to generate PWM wave at perfect timing so that, SPI read with SMP==0 will return 0 and with SMP==1 will return 0xFF ?
Alexander Bessman
@bessman
How precise is "perfect"? Are the frequency and duty cycle constant?
The PSLab's PWG generator has a precision of around 100 ns.
NAVEEN S R
@nkpro2000sr

For testing, we need a PWM wave with the same frequency as SPI and 50% phase shifted from SPI. So that if we read, we get 0 (when SMP=0; Input data is sampled at the middle of data output time) and 0xFF (when SMP=1; Input data is sampled at the end of data output time).

Like:

SCK:   ___|```|___|```|___|``
PWM:   `|___|```|___|```|___|
SMP=0: ___|_______|_______|__  (Input Sample)
SMP=1: _______|_______|______  (Input Sample)
Alexander Bessman
@bessman
The PWM frequency goes up to about 1 MHz, maybe a little bit higher but then the timing starts to be not so great. The frequency of the SPI bus can be lower than that, I believe. Is it sufficient to test up to that frequency?
The phase shift may be tricky. We need to check if there is a constant phase shift between the SPI bus and a PWM signal with the same frequency. If there is, it should be easy to adjust the PWM signal's phase to get the desired behavior. If the phase shift is not constant (i.e. the frequencies are not exactly the same), this method probably won't work.
CyReVolt
@CyReVolt:matrix.org
[m]
I won't make it today
Alexander Bessman
@bessman
@nielek2 I pushed some changes to the TCD1304. Clocks now look like this:
4 replies
Figure_1.png
Zoomed in:
Figure_1.png
CyReVolt
@CyReVolt:matrix.org
[m]

Here's a decent board for those interested in FPGAs:
https://github.com/GlasgowEmbedded/glasgow

And the other one from the Radiona hackerspace:
https://radiona.org/ulx3s/

Both are open hardware and work with open tooling. The Glasgow is very much like PSLab, but based on an FPGA.

Glasgow is a tool for exploring digital interfaces, aimed at embedded developers, reverse engineers, digital archivists, electronics hobbyists, and everyone else who wants to communicate to a wide selection of digital devices with high reliability and minimum hassle. It can be attached to most devices without additional active or passive components, and includes extensive protection from unexpected conditions and operator error.
CyReVolt
@CyReVolt:matrix.org
[m]
Another interesting board:
http://www.gnarlygrey.com/?i=1
And the legendary OrangeCrab:
https://1bitsquared.de/products/orangecrab
CyReVolt
@CyReVolt:matrix.org
[m]

Sooo... they're all based on Lattice FPGAs (Lattice being an FPGA vendor). Arrow is just a distributor, and they do have Lattice among their catalog:
https://www.arrow.com/en/products/lcmxo3lf-9400e-5mg256c/lattice-semiconductor

@mariobehling could you ask the person who contacted you if they would offer their workshop based on the open tooling that the community made for Lattice FPGAs?

And sorry for being quite dismissive... I think that was premature.
Mario Behling
@mariobehling
@CyReVolt:matrix.org Sure, I will ask. Thanks

The Glasgow is very much like PSLab, but based on an FPGA.

Where would you see a difference to what a future PSLab FPGA could offer compared to the Glasgow board?

CyReVolt
@CyReVolt:matrix.org
[m]
I don't see one. The main value I see in PSLab is the apps with the full stack. The key step for someone to get started - in my view - is to learn how wiring things up leads to getting something to show up in the apps. It's that moment when someone realizes "I put this together and understood what it means". And because they have the app, they can focus entirely on the mechanical and analog world. Does that make sense? :-)
And I just got some values out of the TCD1304, I think. I have no idea what they mean though. They range around 3740-3750 or something like that.
Kartikay Sharma
@kartikaysharma01
Can someone with the required rights please make a new branch off the master branch, so that I can open the logic analyzer draft PR against it?
CyReVolt
@CyReVolt:matrix.org
[m]
Just rebase and open the PR against the current one onto upstream kartikaysharma01 (Kartikay Sharma) - it makes no difference
your branch only needs to be applicable to upstream master
CyReVolt
@CyReVolt:matrix.org
[m]
So what I mean is that git is distributed; PRs are just a GitHub thing. I.e., what matters is the patchset, which is what goes to upstream.
CyReVolt
@CyReVolt:matrix.org
[m]
Regarding FPGAs, again:
Esden and others are working on an FPGA demoscene platforn; see https://twitter.com/esden/status/1419894580166598657?s=19 or join on Twitch, where they stream live :)
CyReVolt
@CyReVolt:matrix.org
[m]

From the current chat at gamozo's stream:

It will be a lot of fun. The RISC-V based retro inspired console that drr developed is a great IP to run on this platform. As well as the Doom implementation and a few more things.

nielek2
@nielek2
this could also be interesting open-fpga-wise: https://osfpga.org/events/
100% Open Source FPGA Tools: RTL-to-Bitstream in Minutes - A Hands-On Tutorial
Kartikay Sharma
@kartikaysharma01
The android and desktop versions of the logic analyzer seem very different. Is the android app out of date? Mario once did mention that the android app is more mature. I was just wondering if I should go through the android code too. Will that be necessary?
Kartikay Sharma
@kartikaysharma01
Also, we allow just two channels as a list for the logic analyzer. I believe the reason behind that is because we can map just 2 channels.
2 replies
Kartikay Sharma
@kartikaysharma01
What does the logic_mode disabled indicate?
1 reply
NAVEEN S R
@nkpro2000sr

I have seen the PSLab v{5,6} schematics doc for refactoring UART in pslab-python and I need some clarification for proceeding further.

  1. PSLab v5 uses only one UART port, which is shared for USB, WIFI, BT and External. Right?
  2. Since all of these shares the same port, only one can be used at a time.
  3. UART pass through has no use in v5.
  4. Since WIFI, BT uses the same port as USB, we can send commands and get result directly via wifi or BT. Right?
  5. PSLab v6 uses two UART port, one dedicated for USB and another for WIFI, BT, External.
  6. What is the use of UART pass-through? Is it only used to send commands and get results via wifi or BT, since both are in separate UART port?

Thankyou.

@CloudyPadmal

2 replies
CyReVolt
@CyReVolt:matrix.org
[m]
I can confirm the first 5 points.
nielek2
@nielek2
@nkpro2000sr maybe interesting
TempSense: A Four-Channel Temperature Logger Based on a USB Bridge and CircuitPython https://openhardware.metajnl.com/articles/10.5334/joh.34/

today:
100% Open Source FPGA Tools: RTL-to-Bitstream in Minutes - A Hands-On Tutorial

o Claire Wolf, Inventor of Yosys and Founder/CTO of YosysHQ
o Vaughn Betz, Professor & NSERC/Intel Industrial Research Chair at University of Toronto
o Xifan Tang, Research Assistant Professor at University of Utah & Lead Developer of OpenFPGA Project

register here: https://us02web.zoom.us/webinar/register/WN_WUps_z07T3GV2LDqsnSSJA?timezone_id=Europe%2FBerlin

Kartikay Sharma
@kartikaysharma01
As the final GSoC evaluations start on 16th, is there a preferred platform for the final report? I personally would prefer Github Gist.
2 replies
Mario Behling
@mariobehling
Here is another multi-tool based on Arduino.
QUARK: Open Source Handheld Electrical Measurement Probe based on ESP32 and Arduino
https://circuitstate.com/featured/quark-open-source-handheld-electrical-measurement-probe-based-on-esp32-and-arduino/#comments