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    Anthony Cerruti
    @srnb_gitlab

    Hey all, I couldn't find an answer anywhere else, so I'm gonna try to ask here:

    The code I'm developing is meant to be run on a TinyFPGA BX, and I want to be able to have one physical microUSB port that connects to both the FPGA as well as code I'm putting on the FPGA. Is this possible? How many pins on the FPGA will I need to dedicate for it?

    Jack Koenig
    @jackkoenig
    @gxlong1983, I don't know much about the RISC-V spec actually, you'll probably have more luck on the isa-dev mailing lists: isa-dev@groups.riscv.org
    @colin4124 the logic is slightly simpler to just emit UInt literals and cast. Since FIRRTL compilation will clean it up anyway, it doesn't really matter
    I can't remember exactly when/why we did that but it gives the same result
    @srnb_gitlab, unfortunately I don't know anything about actually using the TinyFPGAs, just that they look cool :slight_smile:, you might have more luck on one of Luke Valenty's repos: https://github.com/tinyfpga
    Leway Colin
    @colin4124

    AsyncReset doesn't support non-literal 'asSInt(UInt<1>("h1"))' as reset alue. How do I solve it? Change FIRRTL to let AsyncReset support non-literal, or change Chisel to generate SInt literal?

    AsyncReset Reg 's_reg' reset to non-literal 'asSInt(UInt<1>("h1"))'

    class RegInitAsyncCase extends RawModule {
      val clock = IO(Input(Clock()))
      val reset = IO(Input(AsyncReset()))
      val in    = IO(Input(UInt(8.W)))
      val s_out = IO(Output(SInt(8.W)))
    
      val s_reg = withClockAndReset(clock, reset) { RegInit(-1.S)}
    
      s_reg := in.asSInt
      s_out := s_reg
    }
    Jack Koenig
    @jackkoenig
    We should fix InferResets in FIRRTL
    This is an oversight
    Leway Colin
    @colin4124
    Thanks, I got it ^_^
    Jack Koenig
    @jackkoenig
    Yeah sorry about that :slight_smile:
    xklqj
    @xklqj
    image.png
    how should I give different defination acording diferent paramter?
    xklqj
    @xklqj
    image.png
    why this error hanppened?
    it doesn't say where go wrong
    xklqj
    @xklqj
    image.png
    xklqj
    @xklqj
    I can not go on my work without solve this problem, does anyone know about it ?
    Leway Colin
    @colin4124
    Could you provide smallest testcase, which reproduce this problem. I try to help debug it.
    xklqj
    @xklqj
    class ram_34x480_Box extends BlackBox with HasBlackBoxResource {
    val io=IO(new Bundle {
    val rsta=Input(Reset())
    val clka=Input(Clock())
    val addra=Input(UInt(6.W))
    val dina=Input(SInt(480.W))
    val douta=Output(SInt(480.W))
    val wea=Input(Bool())
    })
    addResource("/ram_34x480.v")}
    class ram_34x480(achieve:Int)extends Module{
    val io = IO(new Bundle() {
    val addra = Input(UInt(10.W))
    val dina = Input(SInt(480.W))
    val douta = Output(SInt(480.W))
    val wea = Input(Bool())
    })
    if (achieve == 1) { // achieve by FPGA IP using BlackBox
    val ram = Module(new ram_34x480_Box)
    ram.io.rsta:=Wire(Reset())
    ram.io.clka:=Wire(Clock())
    ram.io.addra:=io.addra
    ram.io.dina:=io.dina
    io.douta:=ram.io.douta
    ram.io.wea:=io.wea }
    else {io.douta := 0.S;}
    }
    object King2 extends App {
    chisel3.Driver.execute(args, () => new ram_34x480(1)) }
    runMain King2
    nhvlong
    @nhvlong
    Dear all, I'm new in using Chisel3. Before using Chisel3 as a part of my work, I need to identify well (and of course to present well) about the State of the Art of using Chisel3. In particular, I want to know what is the precisely benefits of Chisel3? It will be great if somebody here could give me a list of papers, articles or even journals that mention about Chisel3. Thanks a lot :)
    Leway Colin
    @colin4124
    class ram_34x480_Box extends BlackBox with HasBlackBoxResource {
      val io=IO(new Bundle {
                  val rsta=Input(Bool())
                  val clka=Input(Clock())
                  val addra=Input(UInt(6.W))
                  val dina=Input(SInt(480.W))
                  val douta=Output(SInt(480.W))
                  val wea=Input(Bool())
                })
      addResource("/ram_34x480.v")
    }
    
    class ram_34x480(achieve:Int)extends Module{
      val io = IO(new Bundle() {
                    val addra = Input(UInt(10.W))
                    val dina = Input(SInt(480.W))
                    val douta = Output(SInt(480.W))
                    val wea = Input(Bool())
                  })
      if (achieve == 1) { // achieve by FPGA IP using BlackBox
        val ram = Module(new ram_34x480_Box)
        ram.io <> DontCare
        // ram.io.rsta := Wire(Reset())
        // ram.io.clka := Wire(Clock())
        ram.io.addra:=io.addra
        ram.io.dina:=io.dina
        io.douta:=ram.io.douta
        ram.io.wea:=io.wea }
      else {io.douta := 0.S;}
    }
    
    object King2 extends App {
      chisel3.Driver.execute(args, () => new ram_34x480(1))
    }

    @xklqj The problem is that

        ram.io.rsta := Wire(Reset())
        ram.io.clka := Wire(Clock())

    You should connect clock and reset, not the type declaration.

    If you just want DontCare, val rsta=Input(Bool()) must be Bool not Reset(), because Reset() can connect DontCare.

    Leway Colin
    @colin4124
    s/can/can't
    xklqj
    @xklqj
    thank you very much!!! the problem has been solved!!!
    xklqj
    @xklqj
    image.png
    I am try to run a test program, why this error happen? I have not poke or peek on any Analog IO
    ChanForPres
    @ChanForPres
    is sdx actually an instruction?
    cant seem to find it on any specs
    referring to this line
    sdx9, 96(x22)// Stores h + A[8] back into A[12]
    ?
    David Durst
    @David-Durst

    Hi All,

    I'm new to Chisel and I'm having an issue with elaboration running out of memory. For example, one of my smaller designs requires Java's Xmx parameter to be 4G. This is unsustainable as my larger designs require Xmx >10GB. Do you all have any advice for how to write more efficient Chisel?

    You can see one of my smaller designs at: https://bit.ly/2vbfef3.

    The design creates a lot of nested Chisel modules. My intuition is that my high memory utilization may come from all the modules that I'm initializing. Should I convert my map and reduce into an inline form like https://github.com/freechipsproject/chisel3/blob/master/src/main/scala/chisel3/util/Counter.scala? Are there other steps I can take?

    The logs from running the design with 2GB for Xmx is:

    stdout:
    Run starting. Expected test count is: 1
    TopTester:
    Top
    [info] [0.001] Elaborating design...
    stderr:
    Exception: java.lang.OutOfMemoryError thrown from the UncaughtExceptionHandler in thread "ScalaTest-main"

    Thank you for your help!

    画面
    @redpanda3
    @David-Durst How come 10GB...
    Schuyler Eldridge
    @seldridge
    @nhvlong: Welcome to the community. Benefits are difficult to answer in a way that people will understand/accept... You may want to consult this Stack Overflow question/answer: https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages/53011766. I view it as Chisel (or things like Chisel) being more "powerful" than synthesizable Verilog/SystemVerilog/VHDL. You're layering software paradigms on top of hardware design.
    For open source projects using Chisel, the website has some known projects listed: https://www.chisel-lang.org/community#projects-using-chiselfirrtl. For more strictly academic work you may luck doing a search on Google Scholar for who's cited the original Chisel paper: https://scholar.google.com/scholar?cites=1523926639711227948&as_sdt=5,33&sciodt=0,33&hl=en.
    Schuyler Eldridge
    @seldridge
    @David-Durst: hi, and also welcome! It looks like this pattern in aetherling is creating a lot of modules. Each module, in Chisel, does create a new object. So doing that heavily will drive up memory usage. "Large" designs will have large memory requirements during elaboration. I've heard that SiFive has larger SoC designs that may need 64GB to get through (perhaps higher).
    It would probably be a good idea to have an idea of how many modules you're creating and to either see where you don't have to create modules. You may also consider looking at an experimental API for cloning modules chisel3.experimental.CloneModuleAsRecord (See: https://www.chisel-lang.org/api/latest/chisel3/experimental/package$$CloneModuleAsRecord$.html, https://github.com/freechipsproject/chisel3/pull/943).
    For the style that you're using you may also consider Chisel's inlining/flattening APIs. These won't help with elaboration as inlining/flattening are FIRRTL transforms, but they will reduce the module nesting in the resultant Verilog (assuming that's what you want). See: https://www.chisel-lang.org/api/latest/chisel3/util/experimental/InlineInstance.html, https://www.chisel-lang.org/api/latest/chisel3/util/experimental/FlattenInstance.html
    David Durst
    @David-Durst
    @redpanda3
    1. I'm running it on my desktop. I wasn't actually able to elaborate my larger design. I just know that it wouldn't run with 10GB.
    2. I'm concerned with scaling. If going to larger designs increases RAM utilization by at least > 2.5x, I'm concerned that even larger designs would require require 100s GB of RAM.
      100s GB of RAM for my largest designs doesn't seem reasonable since I know that much more complicated chips have been written in Chisel than mine.
    Schuyler Eldridge
    @seldridge
    What you have may be a perfect case for CloneModuleAsRecord. Stuff like (https://github.com/David-Durst/chiselAetherling/blob/46ed0bcad820c9ea4ac81fa9620dae12bc02b59c/src/main/scala/aetherling/modules/higherorder/MapS.scala#L8) where you're constructing n copies of some module.
    David Durst
    @David-Durst
    @seldridge
    Thank you!
    Makes sense. A rough estimate is that https://bit.ly/2vbfef3 creates >500 modules. Is there a pass in Chisel that does this counting?
    As a rule of thumb, when should I make a module? It seems like all modules could be rewritten to be functions accepting and returning tuples of data objects. If that's more efficient, why not just write everything that way?
    I'll try rewriting my code to use chisel3.experimental.CloneModuleAsRecord. If that doesn't work, I can implement my operators as functions. I don't think any of my operators actually need to be a module.
    The flattening/inlining APIs look very helpful. I've had issues in Verilator where cc1plus or clang runs out of memory. I thought (though had no conclusive evidence) that this was due to excessive hierarchies. I'll try that out once I get the elaboration times down.
    Schuyler Eldridge
    @seldridge
    @David-Durst: There's no pass doing that. We can add some debugging information to list modules as they're created in the Module object.
    Schuyler Eldridge
    @seldridge
    When to create a module is usually guided by either a need for encapsulation (you want to expose some unit of hardware only via its IO analogous to a software API) or if you reuse it or think others will reuse it. If you do a pure flat design then the description of the hardware is going to be way larger due to duplication of common components. Not a great answer.
    David Durst
    @David-Durst
    @seldridge I see, thanks for the advice! chisel3.experimental.CloneModuleAsRecord helped significantly. However, it didn't seem like flattening or inlining had much of an effect.
    Schuyler Eldridge
    @seldridge
    @David-Durst: Hey, that's good. Flattening/Inlining is an API that will cause FIRRTL transforms to run. This won't help with elaboration as you will still emit one module for every instantiation at the Chisel level. That would only help with generating possibly cleaner Verilog at the output.
    Fernando Cladera
    @fcladera
    Hi guys! I am a new in chisel, and I have been working in some simple designs. I really love the tool!
    I have a small issue that I have not been able to figure out so far. Is there an easy way to infer a bram from a Queue object? So far, ISE (we have spartan 6 dev boards) infers LUT memories from queues