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    Verneri Hirvonen
    @chiplet

    Is there any way to iterate over the ChiselEnum enumeration names and values? Looking at the chipsalliance/chisel3#885 for the feature, MyEnum.Values was the proposed syntax for iterating over the values. However, this does not compile and I cannot find a definition for Value in the source either.

    I'm using ChiselEnum to encode instruction types, and I'm now writing a module that would parse human readable ASCII strings from the different enumeration values.

    This is some pseudocode for the approach I was thinking of:

    def ascii_bits(message: String): Bits = ("h"+message.map(c => "%02x".format(c.toByte)).mkString).U
    
    class DebugInstrText extends Module {
        val io = IO(new Bundle {
            val instr = Input(Instruction())
            val instr_text = Output(Bits(48.W))
        })
    
        io.instr_text := ascii_bits("xxxxxx")
        for (i <- Instruction.Values) {
            when (io.instr === i) {
                io.instr_text := ascii_bits(instr_names[i])  // instr_name is an array/map with the corresponding strings
            }
        }
    }

    I would appreciate any feedback about how to achieve this, or if there exist workarounds/better alternatives for achieving similar functionality.

    7 replies
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    If you want to take a look on how I do in my blinky example: https://github.com/carlosedp/chisel-playground/blob/master/blinky/build.sbt
    6 replies
    awesome!
    👍🏻
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    but became a bit confusing
    Tong Wu
    @Quarky93
    just thinking... 🤔 I want to make a FPGA library for chisel and adding some pseudo-HLS features (perhaps as a different library) to it, i.e. auto-pipelining.
    2 replies
    is it possible to write a firrtl pass that for every module emits the verilog, runs synthesis/PnR (e.g. yosys/nextpnr or vivado) and inserts registers depending on the results?
    1 reply
    Tong Wu
    @Quarky93
    something like PipelineC https://github.com/JulianKemmerer/PipelineC but as a firrtl pass
    Tong Wu
    @Quarky93
    for vivado, you could use the rapidwright interface to invoke synthesis / PnR and even manipulate netlists all from within java
    Oron Port
    @soronpo
    They use FIRRTL
    It will be discussed this week during the LATTE workshop at ASPLOS https://capra.cs.cornell.edu/latte21/
    Peter Aaser
    @PeterAaser
    Has anyone here ever used chisel for SAT?
    We want to use SAT for our compiler, and I realized that since the prototype is implemented in chisel, maybe it's possible to just lift the part of the CPU we want to run SAT on
    Since circuits is a typical input for SAT solvers that's a fairly natural transformation, what do you think?
    Peter Aaser
    @PeterAaser
    Come to think of it, this is pretty close to what verifiers do
    as in, given a circuit, is there any sequence of inputs that can put it in an error state
    so much of the infrastructure must be there already
    9 replies
    Tong Wu
    @Quarky93
    @soronpo Oh that's very cool, I hope there will be an open source example!
    Andrew Dobis
    @Dobios
    Hi, I would like to submit a talk for this year's Chisel Community Conference. I saw that the Call for Speakers has been out since March 29th but I can't seem to find a link anywhere, could anyone help me with that?
    2 replies
    XinJun Ma
    @itviewer

    The IntelliJ Diagrammer plugin is now free and open source.
    If you haven’t heard of this plugin, its function is to visualize your Chisel/Firrtl design in an interactive diagram.
    the code, https://github.com/easysoc/easysoc-diagrammer
    download url, https://plugins.jetbrains.com/plugin/16255-easysoc-diagrammer

    Hope it will be helpful for understanding those circuit designs based on Chisel.

    William Wulff
    @WilliamWulff
    Hello. I am currently working with a mixed language project and I was wondering whether any of you had some experience integrating VHDL modules in Chisel, using the VCS backend for mixed language simulation. I attempted - somewhat naively - to create a BlackBox instance of a VHDL module and run that though a Chisel tester as an example, but ran into problems with VCS. As far as I understand, the VCS Backend in Chisel is set up to use a two step flow which works fine for Verilog, but is not sufficient for VHDL. At the moment, when trying to test this example project, VCS parses the VHDL files as if they were Verilog sources which is not quite what I intended.
    1 reply
    Tong Wu
    @quarky93:matrix.org
    [m]
    Matrixafied
    Muhammad Hadir Khan
    @hadirkhan10
    @jackkoenig there is something weird about the Chisel documentation page regarding memories (https://www.chisel-lang.org/chisel3/docs/explanations/memories.html). Seems like the code is not being correctly highlighted in code blocks. Don't know if this has something to do with my browser or others are facing the same issue.
    1 reply
    Peter Aaser
    @PeterAaser
    I see triple backticks where they shouldn't be
    So I can confirm it renders wrong on my machine too
    Muhammad Hadir Khan
    @hadirkhan10

    @carlosedp I have some question regarding the inline memory construct in Chisel. I have the following version of Chisel: 3.4.3. I am trying to import the following statement:

    import firrtl.annotations.MemorySynthInit

    However the Intellij IDE cannot import the statement and shows error.

    However, this import statement works just fine:
    import chisel3.util.experimental.loadMemoryFromFileInline
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    ah, you need to use chisel3 version 3.5-SNAPSHOT
    Muhammad Hadir Khan
    @hadirkhan10

    I have the following in my build.sbt:

    libraryDependencies ++= Seq(
          "edu.berkeley.cs" %% "chisel3" % "3.4.3",
          "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test"
        ),

    what should I write instead of 3.4.3?

    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    "edu.berkeley.cs" %% "chisel3" % "3.5-SNAPSHOT",
    Jack Koenig
    @jackkoenig:matrix.org
    [m]
    Rather than using 3.5-SNAPSHOT which contains unrelated breaking changes (and will have more arbitrarily), I would suggest using 3.4-SNAPSHOT which you can think about as "To be released as 3.4.4 with perhaps some other non-breaking changes"
    Oh and 3.5-SNAPSHOT will not work with chiseltest v0.3.3, you'll need chiseltest 0.5-SNAPSHOT which may or may not be autopublished yet (mea culpa 😰)
    Muhammad Hadir Khan (Gitter): to summarize, I'd suggest changing your chisel3 dependence to "edu.berkeley.cs" %% "chisel3" % "3.4-SNAPSHOT",, you'll also need to add resolvers += Resolver.sonatypeRepo("snapshots") so that SBT looks in the right place for SNAPSHOTs
    1 reply
    Muhammad Hadir Khan
    @hadirkhan10
    okay thanks @carlosedp and @jackkoenig:matrix.org
    1 reply
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    To fix the doc formatting I've submitted chipsalliance/chisel3#1863
    1 reply
    Jack Koenig
    @jackkoenig:matrix.org
    [m]
    memories doc page has fix merged, thanks Carlos Eduardo de Paula ! Assuming the bots do their thing, the fix should be live on the website by tomorrow
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    That's great Jack Koenig
    Thanks!!
    Muhammad Hadir Khan
    @hadirkhan10

    I am trying to create a parameterized maskable ram, which means I would need an if condition to generate Inputs as Vec (for masked write) and an additional mask signal of type Vec (for masking) or a simple UInt (incase parameter maskable is false). Here is how I am going with it following the optional bundle creation I found on StackOverflow:

    class BlockRamBundle(addrWidth: Int, dataWidth: Int, maskable: Boolean) extends Bundle {
      val addr = Input(UInt(addrWidth.W))
      val write = Input(Bool())
      val enable = Input(Bool())
      val mask = if(maskable) Some(Input(Vec(4, Bool()))) else None
      val wrData = if(maskable) Some(Input(Vec(4, UInt((dataWidth/8).W)))) else Some(Input(UInt(dataWidth.W)))
      val rdData = if(maskable) Some(Output(Vec(4, UInt((dataWidth/8).W)))) else Some(Output(UInt(dataWidth.W)))
    }
    class BlockRam(
                    addrWidth: Int,
                    dataWidth: Int,
                    maskable: Boolean,
                    programFile: Option[String]) extends Module {
    
      val io = IO(new BlockRamBundle(addrWidth, dataWidth, maskable))
    
      val mem = if (maskable) {
        SyncReadMem(Math.pow(2, addrWidth).toInt, Vec(4, UInt((dataWidth/8).W)))
      } else {
        SyncReadMem(Math.pow(2, addrWidth).toInt, UInt(dataWidth.W))
      }
    
      if(programFile.isDefined) {
        loadMemoryFromFile(mem, programFile.get)
      }
    
      io.rdData := mem.read(io.addr, io.enable)
      when(io.write) {
        if(maskable)
          mem.write(io.addr, io.wrData.get, io.mask.get)
        else
          mem.write(io.addr, io.wrData.get)
      }
    
    }

    But, I am getting this error with the mem.read function:

    type mismatch;
    [error]  found   : (some other)_1(in value mem)
    [error]  required: _1(in value mem)
    [error]   io.rdData := mem.read(io.addr, io.enable)

    and this error on mem.write function:

    type mismatch;
    [error]  found   : chisel3.Data
    [error]  required: _1
    [error]       mem.write(io.addr, io.wrData)

    How can I resolve this issue or what other approach is possible?

    18 replies
    Muhammad Hadir Khan
    @hadirkhan10
    Btw @jackkoenig what is the difference b/w creating a ROM with VecInit or with SyncReadMem that has no write port and just a loadMemoryFromFile construct. Are there any differences in terms of the FIRRTL emitted and later porting on the FPGA or taking to the ASIC?
    8 replies
    banality
    @banality
    Hello, Is there, Nowadays, a good way of creating an array of Modules that can be dynamically indexed by hardware signal?
    Quarky93 (Tong Wu)
    @quarky93:matrix.org
    [m]
    val modules = VecInit(Seq.fill(8) { Module(new MyModule).io })
    you can have a Vec of IO bundles
    it's not ideal but that's the way i've been doing it
    banality
    @banality
    @quarky93:matrix.org OK, thank you.
    Quarky93 (Tong Wu)
    @quarky93:matrix.org
    [m]
    I guess you could also put the modules themselves in an array and then put their ios in another Vec which is hardware indexable
    That way you don’t lose the module objects themselves in case you need some field information in them
    A computed latency field perhaps
    banality
    @banality
    Thanks, I know that