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    Liwei Ma
    @davidmlw
    Not really. treadle is the key of simulation and verification. testing style is the last thing.
    Schuyler Eldridge
    @seldridge
    Ah, I think I'm understanding... You want the ability to package up the VIP and hook it up to whatever dut/IP you want? There was a discussion about the ability to reuse a testers2 test with a Verilog blackbox. (This came up as there were requests for testing later stage Verilog, see: ucb-bar/chisel-testers2#60)
    I'm inspecting this too, it should be a bug that tester2 drop all annotation somewhere:(
    Liwei Ma
    @davidmlw
    not only the DUT is a blackbox, but the VIP is a blackbox. Testbenches are higher than a DUT IP, while VIP is equal to a DUT.
    that is the difference.
    chisel provides a way to descibe IP, and we need a way to describe VIP, not test bench.
    Schuyler Eldridge
    @seldridge
    And an example of VIP would be something like a USB bus functional model?
    Liwei Ma
    @davidmlw
    Yes, good example.
    Sequencer
    @sequencer
    @chick It didn't honor the logger.LogLevelAnnotation(logger.LogLevel.Trace)), I have to use print test to find where did it lost all annoations:(
    Liwei Ma
    @davidmlw
    we dont need write the VIP in testbench. we just instantiate one and connect to an phyiscal IP.
    Schuyler Eldridge
    @seldridge
    @davidmlw: Okay, I think I'm beginning to understand. Thanks for being patient.
    Sequencer
    @sequencer
    @davidmlw another question is that how can we implement a ScalaBlackBox in tester2(no only treadle), I think tester2 should target to multi backend
    Liwei Ma
    @davidmlw
    I'd like to discuss with you
    Schuyler Eldridge
    @seldridge
    (And the better people to discuss with are Richard and Adam... If you want to write up some of these ideas in an RFC on the Testers2 repo, that would be great.)
    Sequencer
    @sequencer
    That the key issue I think.
    Liwei Ma
    @davidmlw
    that is why I mentioned treadle, not iotester2. @sequencer . Treadle is the important one.
    Sequencer
    @sequencer
    I got it.
    Liwei Ma
    @davidmlw
    Why treadle is important? it provide parallel and cloud simulation other than property tools. VIP is a sub-problem of treadle. All the verification logic and test vectors and assertions happen in VIP. Scala test framework is just a container of the test case names, and has been well done.
    @seldridge good suggestion, I will
    mitch1993
    @mitch1993
    Hello!
    Schuyler Eldridge
    @seldridge
    :wave:
    mitch1993
    @mitch1993
    i‘m working with an older dev version of Chisel which I modified. When trying to divide FixedPoint numbers I get an error that says division is illegal on FixedPoint types. Was this fixed recently or is it still not possible?
    Liwei Ma
    @davidmlw
    Another suggestion is that Chisel absort rocket.config and LazyModule system in Chisel.
    @davidmlw: That's reasonable. That is now a separate repo, right? (https://github.com/chipsalliance/api-config-chipsalliance/tree/master ?) I expect it would be reasonable if SiFive started to publish that.
    Liwei Ma
    @davidmlw
    Yes, config is separated now, LazyModule is not yet.
    Schuyler Eldridge
    @seldridge
    Diplomacy is another animal...
    Liwei Ma
    @davidmlw
    Diplomacy and tilelink should remains library or in rocket
    while LazyModule is a language thing
    Schuyler Eldridge
    @seldridge
    My understanding is that LazyModule is diplomacy-specific and wouldn't be something that a user would need unless they were using diplomacy. Did you have some other idea in mind?
    Sequencer
    @sequencer
    LazyModule is depend on diplomacy, I think
    Liwei Ma
    @davidmlw
    In my understanding, the node thing is the acctual diplomacy thing. The LazyModule and ModuleImp scheme is just a two-phase language capability. Only my opinion.
    Sequencer
    @sequencer
    Yes, so without the concept of two-phase generation idea by diplomacy, standalone LazyModule seems to be useless?
    Schuyler Eldridge
    @seldridge
    There's also a large refactor of Chisel and FIRRTL to structure these as stages composed of phases. This lets you stack phases that would run before/after elaboration. So, if you wind up needing to add phases or do n-phase elaboration (and solving a different problem than parameter negotiation which diplomacy does well!), this may be a framework to build that.
    Sequencer
    @sequencer
    I think phase-based chisel elaboration would be a great idea :)
    Liwei Ma
    @davidmlw
    This is a better solution
    @sequencer I think you mentioned a good point, iotester needs support different backend.
    but how a VIP in scala/chisel can be supported by Verilator is a real problem. that is also a treadle question.
    Sequencer
    @sequencer
    Yes, I think we should port ScalaBlackBox into tester2, for better integration with vcs, since treadle can not handle post-par simulation, while vcs can
    Liwei Ma
    @davidmlw
    Which is how Treadle VIP co-simulated with Verilator or C++.
    Sequencer
    @sequencer
    using vpi for vcs and verilator might works
    @chick I found the problem, I will send a PR to tester2 later.
    Liwei Ma
    @davidmlw
    since Chisel has release to 3.2.0, chisel.iotesters2 needs some updates.
    for example
    symbol 'type chisel3.experimental.MultiIOModule' is missing from the classpath
    Liwei Ma
    @davidmlw
    after some time trial of iotesters2. I didn't find a good way to execute it in a standalone project. I just filed an issue in iotester2.
    I will try this in another time. to me, iotesters(2) is the interface for treadle, so I will continue to use iotesters for some while.
    dingbig
    @dingbig
    I love chisel