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    Paulo Costa
    @pcesar22

    I'm trying to create a "register table" in Scala to generate the contents of a transaction based on a known register map with defined names and bitfields I'm looking for a good way to represent all the registers, fields, default values, etc in Scala for consumption by transactor classes that will actually create and drive the SPI/I2C transactions

    As an example, let's use the https://invensense.tdk.com/products/motion-tracking/6-axis/mpu-6500/ register map. Register 101 is I2C Slave 2 Data Out. It is R/W, has a reset value of 0x00. Has 7 bits, each with a bit index, name, and function description. What is a good, practical way to pass that type of data into a Scala data structure?

    Jack Koenig
    @jackkoenig
    @pcesar22 It's not really documented, but rocket-chip provides a standard way using it's Diplomacy library. Whether or not you want to bite the bullet to leverage it, you might at least draw some inspiration form the RegMap API, for example I2C from sifive-blocks: https://github.com/sifive/sifive-blocks/blob/c1dee8234c23c8fc454108e59ecba20987f95cde/src/main/scala/devices/i2c/I2C.scala#L544
    Now this gets complex because it's integrated with Diplomatic interconnect generation including support for multiple buses (TileLink, APB, AXI4) so there's a lot of abstraction
    @cousteaulecommandant async reset is supported as of 3.2.0
    Jack Koenig
    @jackkoenig
    We don't have any special support for register enable. I'm not familiar with the tradeoff of a higher fanout soft-clock enable vs. normal clock gating, but to my knowledge, most Chisel users just go for clock gating. There has been discussion of using FIRRTL transforms to transform clock gating into clock enable, especially for FPGA emulation, so perhaps soft-clock enable is a more common pattern when targeting FPGAs than ASICs?
    @kammoh I would expect those to work, is FIRRTL itself running?
    For information about reset, see https://www.chisel-lang.org/chisel3/reset.html. It actually focuses more on reset type inference (because that's why I wrote it), but it probably could use another section on just the basics of reset in Chisel
    Kamyar
    @kammoh
    @jackkoenig I just realized I was wrong about ReplSeqMem not running. It actually is executed, and the design has several SeqReadMems in submodules, but during updateMemStmts no DefAnnotatedMemory gets matched. What am I missing here?
    Paulo Costa
    @pcesar22
    Exactly what I was looking for @jackkoenig , thanks!
    Jack Koenig
    @jackkoenig
    @kammoh one pitfall about repl-seq-mem I just remembered, it only supports 1R 1W or 1RW, you can't have any more ports than that, I'm gonna guess you have more ports
    Kamyar
    @kammoh
    1R 1W is what I actually have here
    Jack Koenig
    @jackkoenig
    Interesting
    Could you share a snippet of your FIRRTL in a gist? Or if not could you try making a minimal non-working example?
    Schuyler Eldridge
    @seldridge
    @kammoh: I'm running this here: https://scastie.scala-lang.org/seldridge/844HVJucRIGlebtDBN2kww/251. Scastie/Firefox take a while to generate the log, but ReplSeqMem does run right before LowerTypes.
      ├── firrtl.stage.TransformManager
      │   └── firrtl.passes.InferTypes$
      ├── firrtl.passes.memlib.ReplSeqMem
      ├── firrtl.passes.LowerTypes$
      ├── firrtl.stage.TransformManager
      │   ├── firrtl.passes.ResolveKinds$
      │   ├── firrtl.passes.InferTypes$
      │   ├── firrtl.passes.ResolveFlows$
      │   └── firrtl.passes.InferWidths
    piessteady
    @piessteady_gitlab
    @jackkoenig I actually meant clock gating. If you say most chisel users use clock gating. Do you mean automatic inserted clock gating?
    Or by inserting clock gate instances in chisel code itself?
    Kamyar
    @kammoh
    @seldridge thanks, I realized ReplSeqMem is actually running, but does not match any DefAnnotatedMemory
    That's what I seem to be seeing in debug at least. Also output conf file is empty and the generated verilog contains regular Mem content
    Jack Koenig
    @jackkoenig
    @piessteady_gitlab We (SiFive) at least manually instantiate clock gates in the Chisel code, eg. https://github.com/chipsalliance/rocket-chip/blob/7c072e9999a1be4028aed383dcf97b03e2773988/src/main/scala/rocket/Frontend.scala#L91
    They're treated as BlackBoxes and that we simulate with a model which is replaced with a technology-specific macro in physical design
    Jung Ko
    @kojung
    Hi everyone. I'm new to Chisel and I'm stuck right now, wondering if someone here could help me. I've switched to using chiseltest because I really like the FlatSpec format. However, I can't find the equivalent of --is-verbose flag that exists in iotester framework. Does anyone know how I can turn the verbose flag on? Thanks a lot in advance!!
    Chick Markley
    @chick
    @kojung Try --tr-verbose that should turn on lots of debugging if you are using the treadle backend (which is the default backend)
    Jung Ko
    @kojung
    @chick , I'm using the verilator backend.
    My simplified unit test looks like this:
    import org.scalatest._
    import chisel3._
    import chiseltest._
    import chiseltest.experimental.TestOptionBuilder._
    import chiseltest.internal.VerilatorBackendAnnotation
    
    class FooTest extends FlatSpec with ChiselScalatestTester with Matchers {
        val annos = Seq(VerilatorBackendAnnotation)
        "Foo" should "work" in {
            test(new Foo()).withAnnotations(annos) { dut =>
                ... some tests ...
            }
        }
    }
    and I'm just calling the test inside sbt with testOnly FooTest. Looks like testOnly doesn't like the --tr-verbose flag.
    Chick Markley
    @chick
    @kojung Doesn’t look like chiseltest has quite the same verbose capability as iotesters. What debug are you hoping to see? There is a verilator verbose flag but it doesn’t have an annotation or command line option to turn it on. Right now, you would have to clone that repo and change the hard-coded flag in VerilatorBackend to verbose true. It would probably be a good idea to submit an issue about not being able to turn this on.
    @kojung As an alternative you could use the default treadle backend and just add treadle.VerboseAnnotation to the annotations passed into test(…)
    Jung Ko
    @kojung
    I'm hoping to see the same detail as I would get if I used iotester and passed --is-verbose. Essentially I would like to see the peek/poke values as time progresses. Thanks for your help. Could you point me to the file + line that I need to change? If that works, I'd be happy to submit an issue and all the necessary details.
    Oh... let me try the treadle.VerboseAnnotation.
    Chick Markley
    @chick
    and once again, that will only work with the treadle backend. You’ll get a boat load of output but it can be grep’d to get what you need
    Jung Ko
    @kojung
    Oh, WOW.. treadle.VerboseAnnotation is super verbose.... It printed out the states of all internal wires! :-)
    OK, it's better than nothing. Thank you for your help. If you can point me to the fix for verilator, I can submit an issue.
    Chick Markley
    @chick
    good luck, I will be off-line for a few hours. Just submit the issue saying you want to turn on the debug flags for treadle and verilator, it will be clear enough I think. Cheers
    Jung Ko
    @kojung
    OK, will do. Thanks!
    Paulo Costa
    @pcesar22
    Is there an equivalent function call like "Flipped" but instead of reversing all the directions, change all the directions to "Input"? I'd like to reuse a bundle in a snooping module
    Jack Koenig
    @jackkoenig
    Input will coerce all directions
    same with Output
    claford-v-lawrence
    @claford-v-lawrence
    @kojung Just FYI, io testers can also use flat spec and everything.
    Hrishikesh
    @hrishim_gitlab
    @claford-v-lawrence thank you
    claford-v-lawrence
    @claford-v-lawrence
    No problem:)
    Jung Ko
    @kojung
    @claford-v-lawrence , that's interesting. I'm starting a brand new project with a lifetime of ~1 year. Do you recommend I stick to iotesters + flatspec or should I move to chiseltester in order to be future proof?
    Jung Ko
    @kojung
    @chick , I created ticket freechipsproject/chisel3#1447. I tried my best to capture the context, hopefully it's clear enough what feature I'm requesting.
    Jung Ko
    @kojung
    OK, I switched back to iotester but kept FlatSpec. Everything works fine now and the --is-verbose flag gives me just the right amount of debug information I need to debug my generator. Thanks @claford-v-lawrence for the suggestion, I appreciate it.
    Boris V.Kuznetsov
    @tampler
    @kojung You may take a look at this project. It currently uses iotesters, but delivers a simpler integration and a higher performance test framework, than scalatest
    I'm working on another FIRRTL simulator and will be delivering soon
    claford-v-lawrence
    @claford-v-lawrence
    @kojung Sorry for the delay in response
    Yes, I would recommend (chisel-testers2)[https://github.com/ucb-bar/chisel-testers2]. This is more powerful than iotesters, and I’m currently migrating some of my tests from iotesters to chiseltest
    Oops, my markdown syntax has gone a little rusty