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    Jack Koenig
    @jackkoenig
    Okay, I partially take it back. It is a bug that Chisel is not giving a better error message here, but it is an issue in your code
    The line with the issue:
    illegal_csr_priv := Mux((csr_addr(9,8) > priv_lvl_q.asUInt), true.B, false.B)
                                                        ^
    That .asUInt is on
        val priv_lvl_q = RegInit(pvl.PRIV_LVL_M.asUInt.asTypeOf(new priv_lvl_e()))
    priv_lvl_e is defined as
    class priv_lvl_e extends Bundle
    {
      val PRIV_LVL_M        = "b11"
      val PRIV_LVL_H        = "b10"
      val PRIV_LVL_S        = "b01"
      val PRIV_LVL_U        = "b00"
    }
    It looks like you're trying to use priv_lvl_e as some sort of Enumeration but that's not what Bundles are for, Bundles are structs, not enums
    Jack Koenig
    @jackkoenig
    This message was deleted
    Jack Koenig
    @jackkoenig

    @EdwarDu by default, only for things that implement chisel3.Num, so UInts, SInts and the like:

      val in = IO(Input(Vec(4, UInt(8.W))))
      val out = IO(Output(UInt(8.W)))
      out := in.reduce(_ max _)

    One could build abstractions to apply this to generic types

    @EdwarDu I don't know of anything for checking for overflow, but another thing one could build a generic abstraction for
    Sajjad Ahmed
    @sajjadahmed677
    Thank you @jackkoenig i am looking into it. actually i am confused with implementing chisel nums as we define them in verilog if you could provide a resource regarding chisel enum implementation it would be a great help.
    Jack Koenig
    @jackkoenig
    Sadly I don't think there are much docs on it, but there are some code examples using ChiselEnum: https://github.com/freechipsproject/chisel3/blob/aa2c62248002de97b95523c08d7788e9715e1313/src/test/scala/cookbook/FSM.scala#L21
    It's marked experimental but has been stable
    Sajjad Ahmed
    @sajjadahmed677
    Thank you @jackkoenig
    the_tech_lover
    @69ca9e084e3d4a8_twitter
    Hi, everyone. When I generate verilog from the chisel code, I found my marco definitions in the generated verilog file. I wonder what all these are about?
    3 replies
    Muhammad Hadir Khan
    @hadirkhan10

    @sajjadahmed677 you can use Enums the following way in Chisel:

    val priv_lvl_m :: priv_lvl_h :: priv_lvl_s :: priv_lvl_u :: Nil = Enum(4)

    and then initialize registers through it in the following way:

    val myReg = RegInit(priv_lvl_m)
    or initialize wires through it:
    val myWire = WireInit(priv_lvl_m)

    you can also enclose it inside an object to get better naming and control. You can replicate your above scenario as following:

    object Priv_Lvl_e {
        val priv_lvl_m :: priv_lvl_h :: priv_lvl_s :: priv_lvl_u :: Nil = Enum(4)
    }

    and then access it using the object's property:

    val myReg = RegInit(Priv_Lvl_e.priv_lvl_m)
    Daniel Kasza
    @danielkasza

    Is there a way to dump FIRRTL on a PassException?
    I am currently trying to understand what is causing this:

    Exception in thread "main" firrtl.passes.PassExceptions: 
    firrtl.passes.CheckHighFormLike$UndeclaredReferenceException:  @[test.scala 44:24]: [module TestModule] Reference _T is not declared.
    firrtl.passes.CheckHighFormLike$UndeclaredReferenceException:  @[test.scala 44:24]: [module TestModule] Reference _T is not declared.
    firrtl.passes.PassException: 2 errors detected!

    It happens only when I use my transformation to add cover statements, and it is difficult to debug without seeing what FIRRTL is seeing. :)

    12 replies
    Sajjad Ahmed
    @sajjadahmed677

    Screenshot from 2020-10-28 15-13-36.png

    i am having the following error. why it is saying that the wire is read only.
    https://scastie.scala-lang.org/lXWCLQo8TFSBOwU7YhTDsA

    3 replies
    Gedeon Nyengele
    @thenextged
    @azidar @jackkoenig Keyi, a colleague/teammate at Stanford, would like to contribute his work on source-level debugging for hardware construction languages to the Chisel community. Would the proper channel for an initial discussion be the Chisel dev meeting or an email sent to someone? If it's the latter, who would that someone be?
    Jack Koenig
    @jackkoenig
    @thenextged Chisel dev meetings are probably the right venue. That being said if Keyi wishes to have a smaller initial meeting, I'd be happy to meet with him.
    Also, Alon let me know that Keyi is apparently unable to join the chisel-users Google group. I don't think it used to require "requesting to join" so I've emailed the owner to see if we can get this resolved.
    Gedeon Nyengele
    @thenextged
    @jackkoenig thank you for the quick response. @Kuree let's set up a meeting with Jack and any other interested individuals for maybe an initial discussion and then you can set up a presentation for the Chisel dev meeting.
    1 reply
    Sajjad Ahmed
    @sajjadahmed677
    Hello @jackkoenig i am facing an issue while compiling my chisel code. chisel is excluding some modules when performing verilog
    transforms will you please guide me how can i resolve this issue.
    here the the scastie link of my code.
    https://scastie.scala-lang.org/sajjadahmed677/lyvkVROdRH6B26GDJEjQ9Q/6
    Jack Koenig
    @jackkoenig
    @sajjadahmed677 with such a large example that times out in Scastie, can you instead put it in a Github repo with instructions to reproduce? Also can you provide more information about what you're expecting to see vs. what you are seeing? What modules are missing?
    Sajjad Ahmed
    @sajjadahmed677
    Ok @jackkoenig i will get back to you after uploading it on github repo
    Jack Koenig
    @jackkoenig
    @sajjadahmed677 actually I just noticed that Scastie has a "Download" feature, so no worries on the Github repo
    Just need to understand what the problem is!
    Sajjad Ahmed
    @sajjadahmed677
    That's great @jackkoenig actually when i compile the code chisel excludes PRIM_MIE and MCOUNTER instances which i need to have in generated verilog. Unfortunately couldn't understand that why it is happening. Please guide me the reason or any bug in my code that causes such situation.
    Farzad Farshchi
    @farzadfch
    Can I pass a TLIdentityNode to a module (as an argument) and access its bundle inside the destination module?
    Here I am trying to pass dCacheTap (type: TLIdentityNode) to my module but it gives the following error.
    image.png
    [error] /home/centos/bru-firesim/sim/target-rtl/firechip/boom/src/main/scala/system/BoomSubsystem.scala:54:61: recursive value boomTiles needs type
    [error] val bwRegulator = LazyModule(new BwRegulator(0x20000000L, boomTiles(0).dCacheTap))
    Jesse Cirimelli-Low
    @jcirimel
    Hey everyone! Sorry if you get this question a lot, but I added an annotation to use the --public-flat-rw with Verilator backend to try to whitebox my design with chisel-tester2. This should make all internal wires public, and I believe this is working, but is there anyway to actually peek them within a scala/chisel test bench, or is this something I will need to implement myself? Thanks :)
    4 replies
    vimrc-sj
    @vimrc-sj

    Hello, I have a quick question on the module vector instantiate. How to instantiate a module vector with different parameters? for example, to instantiate a module vector with the same parameter, I am using:

    val u_vec = VecInit(Seq.fill(N)(Module(new abc()).io))

    If I have a parameter array of length N, say para_vec, how to assign the para_vec to the module vector u_vec respectively during instantiate? Thanks a lot.

    Jack Koenig
    @jackkoenig
    Generally you'd use a map:
    val u_vec = VecInit(para_vec.map(p => Module(new abc(p)).io))
    Note that you only need Vec if you're doing dynamic indexing (ie. you want to be able to index in the hardware with wires), Vec requires all elements to be of the same type so if those parameters affect the widths of ports, it will use the max widths of everything in u_vec
    If you don't need to dynamically index, you can just use Scala Seqs which exist only during elaboration time and allow you to operate on the Modules (but no dynamic indexing):
    val myModules = para_vec.map(p => Module(new abc(p)) // Note I don't have to extract the io
    vimrc-sj
    @vimrc-sj
    @jackkoenig Thanks for helping me out. It works well.
    vimrc-sj
    @vimrc-sj

    So basically, I created a class to include the parameters, and use the map function as you said to make it.

    class para_vec{var a: String ="b0000", b: Int=16, c:String="b0000"}
    val p = Array.fill[para_vec](N)(new para_vec())
    val u_vec = VecInit(para_vec.map(p => Module(new abc(p.a, p.b, p.c)).io))

    The problem is then solved. Thanks.

    Bolarinwa Saheed Olayemi
    @refactormyself
    Hello Chisel community, please can I do chisel without sbt. I will just say I don't have any good thing to say about sbt. That is about as polite I can be.
    matrixbot
    @matrixbot
    Schuyler Eldridge 🤣 You can use mill, an alternative build tool, or play around with some single-file Chisel stuff. These are non-standard for most Chisel users, but they are viable. See: https://github.com/edwardcwang/chisel-template-lite or https://github.com/edwardcwang/chisel-single-file. I think Jiuyang Liu (Gitter) is a big mill user.
    Bolarinwa Saheed Olayemi
    @refactormyself
    Thanks, I will check out mill. I was actually hoping someone has tried with bazel.
    1 reply
    Jack Koenig
    @jackkoenig
    Bazel would work, but there aren't examples of anyone doing it AFAIK
    But Chisel really is just a Scala library and now a compiler plugin, both of those features are certainly supported by Bazel Scala rules so it shouldn't be too bad
    Sajjad Ahmed
    @sajjadahmed677
    Hello @jackkoenig will you please guide me about my issue we discussed. It would be a grear help.
    Jack Koenig
    @jackkoenig

    @sajjadahmed677 looking a little bit, I think they're being optimized away because they don't affect the output of the circuit. Using PRIM_MIE as an example, just looking at this connection:

    io.o_error_prim                   := PRIM_MIE.io.o_rd_error

    Later, you override that connection

    io.o_error_prim                        := PRIM_MSCRATCH.io.o_rd_error

    Then again you override it several more times. Only the last connection will win

    This isn't exactly what you're asking (and the answer talks a bit about how to give names rather than keep hardware around), but I talk about some of these issues in this StackOverflow post: https://stackoverflow.com/questions/55401525/how-to-keep-all-variable-name-in-chisel-when-generate-verilog-code
    1 reply
    Note that the section on @chiselName is pre Chisel 3.4, we now have much better naming documented here: https://www.chisel-lang.org/chisel3/docs/explanations/naming.html
    Sajjad Ahmed
    @sajjadahmed677
    Thank you @jackkoenig let me modify the file then i will get back to you. If needed