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    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    something is wonky .. let me test this
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    nope... same error.. created a clean spec:
    import chisel3._
    import chiseltest._
    import org.scalatest._
    import flatspec._
    import matchers._
    
    class StaticModule[T <: Data](ioLit: T) extends Module {
      val out = IO(Output(chiselTypeOf(ioLit)))
      out := ioLit
    }
    
    class TestShouldSpec extends AnyFlatSpec with ChiselScalatestTester with should.Matchers {
      "test" should "test static circuits" in {
        test(new StaticModule(42.U)) { c =>
          // all these work
          c.out.expect(42.U)
          assert(c.out.peek().litValue() == 42)
          c.out.peek().litValue() should be(42)
          // this does not work (but we have been discussing before to maybe make it work)
          // assert(c.out.peek() == 42.U)
        }
      }
    }
    got this:
    [info] compiling 1 Scala source to /Users/cdepaula/repos/chiselv/target/scala-2.13/test-classes ...
    [error] /Users/cdepaula/repos/chiselv/src/test/scala/TestShouldSpec.scala:18:31: discarded non-Unit value
    [error]       c.out.peek().litValue() should be(42)
    [error]                               ^
    [error] No warnings can be incurred under -Werror.
    [error] two errors found
    [error] (Test / compileIncremental) Compilation failed
    any idea on what might be wrong
    Kevin Laeufer
    @ekiwi
    I don't know. This is a warning, so if you remove -Werror you can still compile and execute.
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    I don't have -Werror in scalacOptions...
    ahhh got it
    I was using tpolecat that injected -Werror. ...
    found it....
    it was a warning
    damn
    sbt and etc is kinda hard... thanks Kevin :D
    Kevin Laeufer
    @ekiwi
    Good to hear that things are working now. I am not exactly sure where the warning is coming from. Something returns a value and that value is never used, but not sure which one of the functions is the culprit.
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    gonna look into scalatest issues if I find something
    2 replies
    got it... litValue converts the chisel value back to scala right?
    like 1.U becomes 1 ...
    Kevin Laeufer
    @ekiwi
    yes
    it goes from hardware type (UInt) to software type (BigInt)
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    cool... in practice there is no difference I believe... from "should be" to expect()
    Kevin Laeufer
    @ekiwi
    Yeah. They should essentially do the same. expect does the correct casting for you, so it is a little shorter to write
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    I also loved the .withAnnotations(Seq(WriteVcdAnnotation)) :)
    2 replies
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    ah, so easy to add VCD generation to tests...
    no CLI flags and etc
    or using the Driver.execute... blabla
    Kevin Laeufer
    @ekiwi
    Oh you are coming from PeekPokeTesters .. yeah, glad you like it :)
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    yep!
    so much better!
    I started writing a RISC-V core :)
    Kevin Laeufer
    @ekiwi
    Awesome!
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    and will use all new libs
    it's a learning exercise ... I'm not good at this all... :)
    Kevin Laeufer
    @ekiwi
    If you want to try out using Verilator, you can do .withAnnotations(Seq(VerilatorBackendAnnotation, WriteFstAnnotation))
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    nice!
    I'm following a series of livestreams a friend of mine did where he created a core in Verilog...
    I'm watching to get the concepts and all but writing my own way in Chisel
    Kevin Laeufer
    @ekiwi
    That sounds like an awesome idea.
    Please let us know if any problems or questions come up.
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    Sure I will 😃
    what is the fst annotation?
    1 reply
    one question... can I get a Verilog output for the test spec?
    like.. generate a verilog testbench from chiseltest?
    4 replies
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    Sweet!!! FST output doesn't add all "_BLBLA" signals to GTKWave! 😍
    4 replies
    to the TOP of the module
    yep.. it's kinda messy... I always write a filter in gtkwave...
    like ^[^_.*] or something....
    Kevin Laeufer
    @ekiwi
    I have also been toying with default gtkwave files based on a pass from a community member: https://github.com/ekiwi/chisel-testers2/commits/gtkwave
    So far I haven;t been able to come up with a solution that I think would work for everyone.
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    nice.. gonna try it