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    Jack Koenig
    @jackkoenig
    This is bikeshedding, but I'd do the ceiling op and just create the reg once, something like:
    val clockDiv = {
      val regFreq = if (freq > 5000000) 5000000 else freq
      RegInit(0.U(log2Ceil(regFreq).W))
    }
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    even nicer .... :)
    I like to see these PoVs :)
    there are things so nice in Chisel that I wonder how people do in Verilog and etc...
    Jack Koenig
    @jackkoenig
    They just suffer :slight_smile:
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    In my topmodule, I define both my clock and reset based on board, pll and etc... like this:
      // Instantiate PLL module based on board
      val pll: PLL0 = Module(new PLL0(board))
      pll.io.clki := clock
      // Define if reset should be inverted based on board switch
      val customReset = Wire(Bool())
      if (invReset) {
        customReset := ~reset.asBool()
      } else {
        customReset := reset
      }
    is there a way to have them (the pll clock and this customReset) as my "default" clock and reset that is passed to instantiated modules... so I don't have to do on every module:
      enc.clock := pll.io.clko
      enc.reset := customReset
    1 reply
    ah cool.. wrap everything in my topmodule with it :)
    awesome... thanks again Schuyler Eldridge
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    You got it. Thanks for documenting your progress on Twitter. 😃
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    Yea... having some fun with the new PMOD :)
    it has a LED ring and a rotary encoder...
    writing some samples now...
    sorry about some stupid basic questions...
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    I figured it was something like that... Usually it's: (1) Carlos shows up with a question about $someThing, (2) 4 hours later there's a post on Twitter showing $someThing working. Was laughing about that with the PWM.
    1 reply
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    i was planning to join the dev-call today but got a meeting at the same time..
    loved how the PWM ended up working :)
    you folks really help a lot
    gotta go.. have some dinner!
    thanks again!
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    np
    XinJun Ma
    @itviewer
    https://github.com/easysoc/easysoc-treadle
    An experimental interactive Firrtl simulator based on treadle and wavedrom
    1 reply
    kartikp4892
    @kartikp4892
    Is there any way to skip emitted code for randomising registers?
    1 reply
    Hans Jakob Damsgaard
    @hansemandse
    Can anyone provide a good example on how to use implicit parameters to configure a Chisel module?
    Guy Hutchison
    @hutch31
    Hi, I'm trying to create inputs and outputs programmatically using the Record class. I've gotten to the point where it's trying to create the ports but it's not picking up the data type correctly. I have it coded up here: https://scastie.scala-lang.org/PloKDhbJRYqn3zbGGOXMKw , would appreciate any insights.
    3 replies
    Vladimir Milovanović
    @milovanovic

    Hello everyone,
    we're facing some issues related to SRAM annotations. Currently we are generating blackboxes for SRAM memories inside our modules using the following commands in the Verilog generation App:

    object ModuleNameApp extends App
    {
     val arguments = Array(
        "-X", "verilog",
        "--repl-seq-mem", "-c:ModuleName:-o:mem.conf",
        "--log-level", "info"
      )
      (new ChiselStage).execute(arguments, Seq(ChiselGeneratorAnnotation(() =>new ModuleName)))
    }

    Our module contains a lot of SyncReadMem objects that should be mapped to SRAMs but we do not want to map them all to SRAM. The above commands will generate blackboxes for all SyncReadMems in the design. Actually we want to annotate certain memories to be SRAMs and others to be mapped into registers even though SyncReadMem object is used. We are not sure how to do that but we are certainly sure that is possible to realize. Apologies if somebody has already asked similar question, but it's not that easy to dig it out.

    dbear496
    @dbear496

    I'm using the PeekPokeTester from chisel-iotesters. How do I make the test fail unconditionally? I tried using fail, but then I get an output like

    [info] [1.462] RAN 10000 CYCLES FAILED FIRST AT CYCLE 10000
    ...
    [info] Run completed in 3 seconds, 466 milliseconds.
    [info] Total number of tests run: 1
    [info] Suites: completed 1, aborted 0
    [info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
    [info] All tests passed.
    [success] Total time: 5 s, completed Jun 8, 2021 8:41:32 PM

    Why is it that even after failing, it still passes?

    5 replies
    aicr
    @aicr
    Hi all , I'm looking for an example / explanation on a good way to ram to to a range of address in regmap() . I have a device that should contain ram /memory for internal use , but can also accessible through tilelink bus. Thanks
    4 replies
    totnine
    @totnine
    Are there any teams or projects currently working on p4 to chisel?
    3 replies
    dbear496
    @dbear496
    Some Chisel methods such as chisel3.stage.ChiselStage.emitVerilog and chisel3.iotesters.Driver.execute take an array of main-like arguments. How should I find a list of available arguments and what they do?
    3 replies
    sam-shahrestani
    @sam-shahrestani
    Excuse the usual faux-pas, this is mostly a rocket-chip question. ChiselOutputFileAnnotation dumps in the protobuf format if the file extension is ".pb" (I believe), but rocket-chip hides this annotation to pump in its own generated name from the build+config. I'd like to add a DumpProtobufAnnotation to rocket-chip, does this already exist? If I created such a thing would people be interested in having it in the public repo via PR?
    2 replies
    Maksim Levental
    @makslevental
    what's the correct way to make a module generic on data type and bit width? right now i have stuff like
    class LineBuffer[T <: Bits](val dtype: T) extends Module {
      val dWidth = dtype.getWidth
      dtype.cloneType
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    Hey Jack Koenig .. found the memory mask issue I mentioned in the call: chipsalliance/chisel3#1289
    1 reply
    Maksim Levental
    @makslevental
    is there a way to peek the clock?
    5 replies
    Hans Jakob Damsgaard
    @hansemandse
    Hi all. I am seeing some strange synthesis results from two different implementations of a Chisel module, NeuronEvaluator, in Vivado. This version synthesizes to roughly 53 LUTs, while this version synthesizes to roughly 138 LUTs. Apart from some minor code changes, the modules (should) implement the same hardware. Any ideas for potential explanations?
    5 replies
    Megan Wachs
    @mwachs5
    Hi all, SiFive is hiring for our Chisel development team. We are open to various levels of experience and remote work. https://www.sifive.com/jobs/4541825003/senior-software-engineer-chisel-san-mateo-california-united-states
    Uri Cohen
    @uricohen1112
    Hello, does chisel work on Scala 3/Dotty? If not, when will there be support for this? Thanks!
    Oron Port
    @soronpo
    @uricohen1112 It does not. At the very least it would require rewriting the compiler plugin.
    Jack Koenig
    @jackkoenig
    And the macros
    erling
    @erlingrj

    Hi guys I am trying to do some quite basic peeking/poking in ChiselTest but cant figure out a way to get it right. I want to enqueue a value to a Decoupled interface and check that an output signal changes in the same cycle
    Ex1: Divergent poking/peeking thread

    fork {
    c.io.input.enqueue(chiselTypeOf(c.io.input).bits.Lit(
       _.val -> 1.U
    ))
    }.fork {
    c.io.test.expect(true.B)
    }.join

    Ex2: Fails since "enqueue" ends with "joinAndStep", so peek is a cycle late

    c.io.input.enqueue(chiselTypeOf(c.io.input).bits.Lit(
       _.val -> 1.U
    ))
    c.io.test.expect(true.B)

    Ex3: Peek happens in the right cycle but is checked before the enqueue happens so its invalid

    c.io.test.expect(true.B)
    c.io.input.enqueue(chiselTypeOf(c.io.input).bits.Lit(
       _.val -> 1.U
    ))

    I could of course write my own version of "enqueue" which does not en with joinAndStep but I am a bit confused why the forking version doesnt work

    6 replies
    yxnan
    @yxnan:matrix.org
    [m]
    Hello everyone, I'm looking into the Rocket Chip RoCC example provided by UCB: , when I follows the readme in this repo, it emits some errors
    The whole error message: https://pastebin.com/SBzFrgAx
    Is this repo still capable of running in the latest Rocket? I'm not sure
    yxnan
    @yxnan:matrix.org
    [m]
    :point_up: Edit: Hello everyone, I'm looking into the Rocket Chip RoCC SHA3 example provided by UCB (https://github.com/kammoh/rocc-template) when I follows the readme in this repo, executing make CONFIG=Sha3CPPConfig run-asm-tests, it emits some errors
    :point_up: Edit: Hello everyone, I'm looking into the Rocket Chip RoCC SHA3 example provided by UCB (https://github.com/kammoh/rocc-template)
    When I follows the readme in this repo, executing make CONFIG=Sha3CPPConfig run-asm-tests, it emits some errors
    Kevin Laeufer
    @ekiwi
    Please have a look at the latest chipyard tutorial: https://chipyard.readthedocs.io/en/latest/Customization/RoCC-Accelerators.html
    The repository you are using might be out of date.
    yxnan
    @yxnan:matrix.org
    [m]
    Thanks, I managed to get the rocc interface running