Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Repo info
Activity
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    it's just vanity... not required :)
    Jack Koenig
    @jackkoenig:matrix.org
    [m]
    Do you mean like a nicer interface to use in the Chisel?
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    like that.. so in my module I could use the <> operator to connect my io to this blackbox io aliases
    like define an alias to the IO USER_SIGNAL_TO_GLOBAL_BUFFER as clki for example...
    and clko to the GLOBAL_BUFFER_OUTPUT
    got my point... I could write a wrapper module to do this... just wondering if it's possible in the blackbox itself
    Jack Koenig
    @jackkoenig:matrix.org
    [m]
    This doesn't exist today, but this sounds like something my proposed DataView would solve: https://gist.github.com/jackkoenig/20bffc2e9270386044aba9f00bc82fd5
    You could use .forceName to force the ugly Verilog names while having nicer names in the Chisel, but as I note in that writeup, forceName is not a composable API so while it's okay, it's not great.
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    ah yes.. it's pretty ok
    another q...
    why a statement like ledDrv.io.CURREN := true.B became assign ledDrv_CURREN = 1'h1; and not 1'b1 ?
    Jack Koenig
    @jackkoenig:matrix.org
    [m]
    FIRRTL doesn't represent Booleans, they're just 1-bit UInts
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    ah ok.. I understand that 1 is 1
    just asking :)
    Kyle Hale
    @khale
    @carlosedp:matrix.org for the MemorySynthInit issue here is what I have: https://termbin.com/tbp6
    Here is what I get during compilation:
    [info] compiling 1 Scala source to /home/kyle/iit3503/out/iit3503_lab/compile/dest/classes ...
    [error] /home/kyle/iit3503/src/main/scala/iit3503/RAM.scala:6:8: object MemorySynthInit is not a member of package firrtl.annotations
    [error] import firrtl.annotations.{Annotation, MemorySynthInit}
    [error]        ^
    [error] /home/kyle/iit3503/src/main/scala/iit3503/RAM.scala:45:7: not found: value MemorySynthInit
    [error]       MemorySynthInit
    [error]       ^
    [error] two errors found
    1 targets failed
    iit3503_lab.compile Compilation failed
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    Hi @khale , I believe it was not in latest release... maybe Jack Koenig can chime in about this..
    in the meanwhile, you can use chisel3 version "3.5-SNAPSHOT" that works fine.
    I don't think the PR was backported to firrtl 1.4 which is used by Chisel 3.4.
    Kyle Hale
    @khale
    gotcha thanks
    12 replies
    Verneri Hirvonen
    @chiplet

    Is there any way to iterate over the ChiselEnum enumeration names and values? Looking at the chipsalliance/chisel3#885 for the feature, MyEnum.Values was the proposed syntax for iterating over the values. However, this does not compile and I cannot find a definition for Value in the source either.

    I'm using ChiselEnum to encode instruction types, and I'm now writing a module that would parse human readable ASCII strings from the different enumeration values.

    This is some pseudocode for the approach I was thinking of:

    def ascii_bits(message: String): Bits = ("h"+message.map(c => "%02x".format(c.toByte)).mkString).U
    
    class DebugInstrText extends Module {
        val io = IO(new Bundle {
            val instr = Input(Instruction())
            val instr_text = Output(Bits(48.W))
        })
    
        io.instr_text := ascii_bits("xxxxxx")
        for (i <- Instruction.Values) {
            when (io.instr === i) {
                io.instr_text := ascii_bits(instr_names[i])  // instr_name is an array/map with the corresponding strings
            }
        }
    }

    I would appreciate any feedback about how to achieve this, or if there exist workarounds/better alternatives for achieving similar functionality.

    7 replies
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    If you want to take a look on how I do in my blinky example: https://github.com/carlosedp/chisel-playground/blob/master/blinky/build.sbt
    6 replies
    awesome!
    👍🏻
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    but became a bit confusing
    Tong Wu
    @Quarky93
    just thinking... 🤔 I want to make a FPGA library for chisel and adding some pseudo-HLS features (perhaps as a different library) to it, i.e. auto-pipelining.
    2 replies
    is it possible to write a firrtl pass that for every module emits the verilog, runs synthesis/PnR (e.g. yosys/nextpnr or vivado) and inserts registers depending on the results?
    1 reply
    Tong Wu
    @Quarky93
    something like PipelineC https://github.com/JulianKemmerer/PipelineC but as a firrtl pass
    Tong Wu
    @Quarky93
    for vivado, you could use the rapidwright interface to invoke synthesis / PnR and even manipulate netlists all from within java
    Oron Port
    @soronpo
    They use FIRRTL
    It will be discussed this week during the LATTE workshop at ASPLOS https://capra.cs.cornell.edu/latte21/
    Peter Aaser
    @PeterAaser
    Has anyone here ever used chisel for SAT?
    We want to use SAT for our compiler, and I realized that since the prototype is implemented in chisel, maybe it's possible to just lift the part of the CPU we want to run SAT on
    Since circuits is a typical input for SAT solvers that's a fairly natural transformation, what do you think?
    Peter Aaser
    @PeterAaser
    Come to think of it, this is pretty close to what verifiers do
    as in, given a circuit, is there any sequence of inputs that can put it in an error state
    so much of the infrastructure must be there already
    9 replies
    Tong Wu
    @Quarky93
    @soronpo Oh that's very cool, I hope there will be an open source example!
    Andrew Dobis
    @Dobios
    Hi, I would like to submit a talk for this year's Chisel Community Conference. I saw that the Call for Speakers has been out since March 29th but I can't seem to find a link anywhere, could anyone help me with that?
    2 replies
    XinJun Ma
    @itviewer

    The IntelliJ Diagrammer plugin is now free and open source.
    If you haven’t heard of this plugin, its function is to visualize your Chisel/Firrtl design in an interactive diagram.
    the code, https://github.com/easysoc/easysoc-diagrammer
    download url, https://plugins.jetbrains.com/plugin/16255-easysoc-diagrammer

    Hope it will be helpful for understanding those circuit designs based on Chisel.

    William Wulff
    @WilliamWulff
    Hello. I am currently working with a mixed language project and I was wondering whether any of you had some experience integrating VHDL modules in Chisel, using the VCS backend for mixed language simulation. I attempted - somewhat naively - to create a BlackBox instance of a VHDL module and run that though a Chisel tester as an example, but ran into problems with VCS. As far as I understand, the VCS Backend in Chisel is set up to use a two step flow which works fine for Verilog, but is not sufficient for VHDL. At the moment, when trying to test this example project, VCS parses the VHDL files as if they were Verilog sources which is not quite what I intended.
    1 reply
    Tong Wu
    @quarky93:matrix.org
    [m]
    Matrixafied
    Muhammad Hadir Khan
    @hadirkhan10
    @jackkoenig there is something weird about the Chisel documentation page regarding memories (https://www.chisel-lang.org/chisel3/docs/explanations/memories.html). Seems like the code is not being correctly highlighted in code blocks. Don't know if this has something to do with my browser or others are facing the same issue.
    Peter Aaser
    @PeterAaser
    I see triple backticks where they shouldn't be
    So I can confirm it renders wrong on my machine too
    Muhammad Hadir Khan
    @hadirkhan10

    @carlosedp I have some question regarding the inline memory construct in Chisel. I have the following version of Chisel: 3.4.3. I am trying to import the following statement:

    import firrtl.annotations.MemorySynthInit

    However the Intellij IDE cannot import the statement and shows error.

    However, this import statement works just fine:
    import chisel3.util.experimental.loadMemoryFromFileInline
    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    ah, you need to use chisel3 version 3.5-SNAPSHOT
    Muhammad Hadir Khan
    @hadirkhan10

    I have the following in my build.sbt:

    libraryDependencies ++= Seq(
          "edu.berkeley.cs" %% "chisel3" % "3.4.3",
          "edu.berkeley.cs" %% "chiseltest" % "0.3.3" % "test"
        ),

    what should I write instead of 3.4.3?

    Carlos Eduardo de Paula
    @carlosedp:matrix.org
    [m]
    "edu.berkeley.cs" %% "chisel3" % "3.5-SNAPSHOT",