Chisel/FIRRTL Discussion and Questions. Use the following template for testing/questions: https://bit.ly/3uzUES2
@yoonhyeonjoon Does the code above compile? If so, it is very close to what I normally write nowadays. The only difference is that I don't use an inner class. I just make a bundle next to the module that carries the module name + IO. So if I have
MyMux extends ModuleI will have aclass MyMuxIO extends Bundleto go with it.
I guess your style is a good way to keep the Scala Compiler type checking rule after 2.12 version.
From my point of view, who have encountered Scala/Chisel relatively recently, Depending on type inference of Scala Compiler(under 2.11) is a little dangerous way to build the codes
I wonder in which direction Chisel is going to develop. I believe that the current design pattern of Chisel/Scala is declarative programming even though the way of operating in compiler is functional by Scala basic Philosophy.
if I look into the current Software Language SwiftUI or Android Compose. It will try to directly provide the Viewing UI design by codes(old traditional way was making both UI XLM and Java source and binding it together)
I think that if we can provide like that UI design by Chisel, It will be more convenient for logic designer who wants to use Chisel(I mean.. we can directly see graphics(GraphML-like) of codes).
I wonder if the developers of the Chisel compiler have plans for something like this in the future.
It may be a slightly different story, but an example of what I'm talking about is the image above.
android compose coding style is that.
left side of codes can show directly the layout and I can easily check what i did.
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What's the best practice to compare only some bits of a port? I'm passing expect to a 16 width output, but I only care about the lower 8 bits. Is this ok?
while (gold_vals.hasNext) {
c.clock.step(1)
assert(io.lfsr.peek()(7,0) == gold_vals.next)
}I think I should also probably do a litvalue comparison instead of a uint one
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like below images
Has anyone used the sbt-assembly plugin with Chisel?
My workflow is to generate a fat JAR which builds all the RTL from the command line, which can then be used by the chisel-illiterate. I've previously used Maven to create these but can't figure out how to get Maven builds working with chisel scala plugin required by chisel 3.5.
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cs bootstrap --assembly edu.berkeley.cs::chisel3:3.5.2 -M chisel3.stage.ChiselMain -o chisel3.jarI wonder what chisel's ultimate goal is..
I thought chisel will replace verilog - verification ( with VCS...) by high level language. so... someday many rtl designers will generate IP using chisel and it'll be tested by scalaTest and chisel compiler guarantee of it's operating in physical chip without other verificating tool.
Do my thoughts on Chisel's ultimate goal align with what Chisel is currently trying to do?
If not, is the method of integration tools for connecting to various IPs that exist today the direction of chisel development?
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Hey Everyone!
I am stuck at a point in my design.
When I am giving an address coming from a register to my SyncReadMem module, it is unable to read, while i gave the same address hardocoded it is reading accurately
val addressBits = Reginit(4.U)
val mem = SyncReadMem(16,UInt(32.W))
// it works
mem.read(4.U, true.B)
// it doesnt
mem.read(addressBits, true.B)This is the dummy functionality of basically what i am trying to do.
Is it due to some conceptual error i am doing?
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Hey guys, I am trying to run the StreamingPassthrough example for a DspBlock (https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala). I copied StreamingPassthrough.scala and DspBlocks.scala (from the same directory in chipyard) in to a new folder. I wanted to just try generating verilog of a single DspBlock so I change the StreamingPassthroughBlock to be a concrete class (instead of abstract as before). I then added a new Main:
package chipyard.example
import chisel3._
import freechips.rocketchip.config.Parameters
/**
* An object extending App to generate the Verilog code.
*/
object Main {
def main(args: Array[String]): Unit = {
println("asdasdasdAASDASDA")
implicit val p: Parameters = Parameters.empty
(new chisel3.stage.ChiselStage).emitVerilog((new StreamingPassthroughBlock(UInt(4.W))).module, Array("-td","gen/"))
}
}But when I run "sbt run" I get an Exception:
[info] running chipyard.example.Main
asdasdasdAASDASDA
Exception in thread "sbt-bg-threads-1" java.lang.NoClassDefFoundError: chisel3/MultiIOModule
at java.base/java.lang.ClassLoader.defineClass1(Native Method)
at java.base/java.lang.ClassLoader.defineClass(ClassLoader.java:1010)
at java.base/java.security.SecureClassLoader.defineClass(SecureClassLoader.java:150)
at java.base/java.net.URLClassLoader.defineClass(URLClassLoader.java:512)
at java.base/java.net.URLClassLoader$1.run(URLClassLoader.java:420)
at java.base/java.net.URLClassLoader$1.run(URLClassLoader.java:414)
at java.base/java.security.AccessController.doPrivileged(AccessController.java:691)
at java.base/java.net.URLClassLoader.findClass(URLClassLoader.java:413)
at sbt.internal.ManagedClassLoader.findClass(ManagedClassLoader.java:102)
at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:586)
at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:519)
at chipyard.example.Main$.main(Main.scala:19)
at chipyard.example.Main.main(Main.scala)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
at java.base/jdk.internal.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:78)
at java.base/jdk.internal.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
at java.base/java.lang.reflect.Method.invoke(Method.java:567)
at sbt.Run.invokeMain(Run.scala:143)
at sbt.Run.execute$1(Run.scala:93)
at sbt.Run.$anonfun$runWithLoader$5(Run.scala:120)
at sbt.Run$.executeSuccess(Run.scala:186)
at sbt.Run.runWithLoader(Run.scala:120)
at sbt.Defaults$.$anonfun$bgRunTask$6(Defaults.scala:1983)
at sbt.Defaults$.$anonfun$termWrapper$2(Defaults.scala:1922)
at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
at scala.util.Try$.apply(Try.scala:213)
at sbt.internal.BackgroundThreadPool$BackgroundRunnable.run(DefaultBackgroundJobService.scala:369)
at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(ThreadPoolExecutor.java:1130)
at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(ThreadPoolExecutor.java:630)
at java.base/java.lang.Thread.run(Thread.java:831)
Caused by: java.lang.ClassNotFoundException: chisel3.MultiIOModule
at java.base/java.net.URLClassLoader.findClass(URLClassLoader.java:433)
at sbt.internal.ManagedClassLoader.findClass(ManagedClassLoader.java:102)
at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:586)
at java.base/java.lang.ClassLoader.loadClass(ClassLoader.java:519)
... 30 more
[success] Total time: 11 s, completed Apr 20, 2022, 5:18:59 PMI realize that this could be because at chisel version 3.5 MultiIOModule was deprecated. But I am having dependency problems also if I go bellow version 3.5... Git: https://github.com/jurevreca12/temp_dspblock_example. What should i do?
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@ekiwi was working on adding a basic unit test for the UnpeekableException and seems something's broken with Treadle in the latest snapshot? None of my tests run successfully when working with the main build.sbt now.
I've changed the default versions back to 3.5.2. for chisel3 and 1.5.2 in treadle on my branch and that seems to work. Test looks good https://puu.sh/IW8gu/f6bd16e0eb.png so I'll at least add that to the PR. I might have some time to look at Treadle tomorrow though I don't think I'll be the first to spot what went wrong here.
Everything's still working with:
val defaultVersions = Map(
"chisel3" -> "3.5.2",
"treadle" -> "1.5.2"
)Hello Chiselers,
I am very delighted to announce that we have released v3.5.3 of the various Chisel-related projects (and v3.5.2 in the meantime which I apparently forgot to announce 🙈):
Chisel v3.5.3 - https://github.com/chipsalliance/chisel3/releases/tag/v3.5.3
FIRRTL v1.5.3 - https://github.com/chipsalliance/firrtl/releases/tag/v1.5.3
ChiselTest, Treadle, DSPTools, and Chisel-Testers also had X.5.3 releases, but had no changes other than bumping their dependencies.
Please note that Chisel-Testers are end-of-life, v2.5 will be the last major release for this project. Please migrate to ChiselTest: https://www.chisel-lang.org/chiseltest/migrating-from-iotesters.
~Jack on behalf of the Chisel development team
P.S. My usual Scastie template now using v3.5.3: https://scastie.scala-lang.org/O3LqeVH7SWyIxD7bZRH8hA
package functional
import chisel3.util.{Counter, Enum}
import chisel3.{Bool, Bundle, Module, Output, RegInit, UInt, fromBooleanToLiteral, fromIntToLiteral, when}
class MockClockGenerator(speed : Int) extends Module {
val io = IO(new Bundle {
val clockB = Output(Bool())
})
val high :: low :: Nil = Enum(2)
val state: UInt = RegInit(high)
val (count, wrap) = Counter(true.B, speed)
when(count <= (speed/2).U)
{
state := low
}.otherwise
{
state := high
}
//Successful
when(state === high) {
io.clockB := true.B
}.otherwise{
io.clockB := false.B
}
//<=== It makes error
// switch(state){
// is(high) {
// io.clockB := true.B
// }
// is(low){
// io.clockB := false.B
// }
// }
}
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I am trying to build a minimal example using an diplomatic implementation of the AXI Stream interface. I use the interfaces available in rocket-chip. Anyway, after more than a week of trying I have not been able to get it to work. What I do is build a simple AXIMaster that sets all the outputs to zero, an AXI slave that doesn't do anything and in between I have an AXI Identity node. The error that I get is:
[error] (Compile / run) java.lang.Exception: Unable to use BundleMap.cloneType on class freechips.rocketchip.amba.axis.AXISBundleBits, probably because class freechips.rocketchip.amba.axis.AXISBundleBits does not have a constructor accepting BundleFields. Consider overriding cloneType() on class freechips.rocketchip.amba.axis.AXISBundleBits The code is available at the git: https://github.com/jurevreca12/temp_dspblock_example/tree/axi_stream_example/scala/main.
I've tried posting at least excerpts from it directly to the chat, but It dind't want to work for some reason. Most of the code is in AxiStreamExample.scala, and the generation part is in Main.scala. I appriciate any tips on how to fix this error.
Would this BundleFields clonetype thing break in 3.5? https://github.com/chipsalliance/rocket-chip/blob/master/src/main/scala/util/BundleMap.scala#L108-L119
Was looking at your post at https://stackoverflow.com/questions/72043687/implementing-a-diplomatic-axi-stream-interface-in-chisel-bundlemap-clonetype-e and seeing if I could improve my understanding of cloneType and Bundlefields. Since as far as I'm aware, Chisel is an elaborate constructor system, I'd think there's something missing for the cloning.
I wonder if the 3.5 bump has anything to do with this exception
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Whenever I use
.withAnnotations(Seq(VerilatorBackendAnnotation))It show the error
chiseltest.legacy.backends.verilator.TestApplicationException: test application exit - exit code 134
[info] at chiseltest.legacy.backends.verilator.SimApiInterface.throwExceptionIfDead(SimApiInterface.scala:126)
[info] at chiseltest.legacy.backends.verilator.SimApiInterface.mwhile(SimApiInterface.scala:140)
[info] at chiseltest.legacy.backends.verilator.SimApiInterface.finish(SimApiInterface.scala:362)
[info] at chiseltest.legacy.backends.verilator.VerilatorBackend.run(VerilatorBackend.scala:250)
[info] at chiseltest.internal.Context$.$anonfun$run$1(Testers2.scala:158)
[info] at scala.runtime.java8.JFunction0$mcV$sp.apply(JFunction0$mcV$sp.java:23)
[info] at scala.util.DynamicVariable.withValue(DynamicVariable.scala:62)
[info] at chiseltest.internal.Context$.run(Testers2.scala:158)
[info] at chiseltest.ChiselScalatestTester.chiseltest$ChiselScalatestTester$$runTest(ChiselScalatestTester.scala:71)
[info] at chiseltest.ChiselScalatestTester$TestBuilder.apply(ChiselScalatestTester.scala:33)I am confused with this what does it mean.
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override val desiredName = "Bar" in the class definition . What do I do if I want to instantiate a class and give it a different name, but don't have the permission to edit the original class code ? import chisel3._
import chisel3.stage.ChiselStage
class Foo extends Module {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
})
io.out := ~io.in
//override val desiredName = "Bar" // uncomment this line
}
println((new ChiselStage).emitVerilog((new Foo).suggestName("dd")))
Is there a way to modify the reset value of a Reg after it has been created? My use case is I have a function which defines some registers and wires for each stage of a pipeline, but for the first pipeline stage, a register needs to be initialized to true instead of false and all else stays the same.
I know I could add an 'isFirst' argument to the function, but I'd prefer a solution which just modifies the function output.
I do not believe it works to use when(reset){reg := true.B} because the actual reset will override this connection.
It's also not ideal to completely redefine the register because the function defines some connections to the register that I want to keep.
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