Chisel/FIRRTL Discussion and Questions. Use the following template for testing/questions: https://bit.ly/33esRsD
illegal_csr_priv := Mux((csr_addr(9,8) > priv_lvl_q.asUInt), true.B, false.B)
^.asUInt is on
val priv_lvl_q = RegInit(pvl.PRIV_LVL_M.asUInt.asTypeOf(new priv_lvl_e()))priv_lvl_e is defined as
class priv_lvl_e extends Bundle
{
val PRIV_LVL_M = "b11"
val PRIV_LVL_H = "b10"
val PRIV_LVL_S = "b01"
val PRIV_LVL_U = "b00"
}priv_lvl_e as some sort of Enumeration but that's not what Bundles are for, Bundles are structs, not enums
ChiselEnum: https://github.com/freechipsproject/chisel3/blob/aa2c62248002de97b95523c08d7788e9715e1313/src/test/scala/cookbook/FSM.scala#L21
val myWire = WireInit(priv_lvl_m)you can also enclose it inside an object to get better naming and control. You can replicate your above scenario as following:
object Priv_Lvl_e {
val priv_lvl_m :: priv_lvl_h :: priv_lvl_s :: priv_lvl_u :: Nil = Enum(4)
}and then access it using the object's property:
val myReg = RegInit(Priv_Lvl_e.priv_lvl_m)
Is there a way to dump FIRRTL on a PassException?
I am currently trying to understand what is causing this:
Exception in thread "main" firrtl.passes.PassExceptions:
firrtl.passes.CheckHighFormLike$UndeclaredReferenceException: @[test.scala 44:24]: [module TestModule] Reference _T is not declared.
firrtl.passes.CheckHighFormLike$UndeclaredReferenceException: @[test.scala 44:24]: [module TestModule] Reference _T is not declared.
firrtl.passes.PassException: 2 errors detected!It happens only when I use my transformation to add cover statements, and it is difficult to debug without seeing what FIRRTL is seeing. :)
12 replies
i am having the following error. why it is saying that the wire is read only.
https://scastie.scala-lang.org/lXWCLQo8TFSBOwU7YhTDsA
3 replies
transforms will you please guide me how can i resolve this issue.
here the the scastie link of my code.
https://scastie.scala-lang.org/sajjadahmed677/lyvkVROdRH6B26GDJEjQ9Q/6
[error] val bwRegulator = LazyModule(new BwRegulator(0x20000000L, boomTiles(0).dCacheTap))
4 replies
Hello, I have a quick question on the module vector instantiate. How to instantiate a module vector with different parameters? for example, to instantiate a module vector with the same parameter, I am using:
val u_vec = VecInit(Seq.fill(N)(Module(new abc()).io))If I have a parameter array of length N, say para_vec, how to assign the para_vec to the module vector u_vec respectively during instantiate? Thanks a lot.
Vec if you're doing dynamic indexing (ie. you want to be able to index in the hardware with wires), Vec requires all elements to be of the same type so if those parameters affect the widths of ports, it will use the max widths of everything in u_vec
val myModules = para_vec.map(p => Module(new abc(p)) // Note I don't have to extract the ioSo basically, I created a class to include the parameters, and use the map function as you said to make it.
class para_vec{var a: String ="b0000", b: Int=16, c:String="b0000"}
val p = Array.fill[para_vec](N)(new para_vec())
val u_vec = VecInit(para_vec.map(p => Module(new abc(p.a, p.b, p.c)).io))The problem is then solved. Thanks.
Schuyler Eldridge 🤣 You can use mill, an alternative build tool, or play around with some single-file Chisel stuff. These are non-standard for most Chisel users, but they are viable. See: https://github.com/edwardcwang/chisel-template-lite or https://github.com/edwardcwang/chisel-single-file. I think Jiuyang Liu (Gitter) is a big mill user.
@sajjadahmed677 looking a little bit, I think they're being optimized away because they don't affect the output of the circuit. Using PRIM_MIE as an example, just looking at this connection:
io.o_error_prim := PRIM_MIE.io.o_rd_errorLater, you override that connection
io.o_error_prim := PRIM_MSCRATCH.io.o_rd_errorThen again you override it several more times. Only the last connection will win
1 reply
@chiselName is pre Chisel 3.4, we now have much better naming documented here: https://www.chisel-lang.org/chisel3/docs/explanations/naming.html