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    matrixbot
    @matrixbot
    seldridge Oh yeah.
    Baltazar Ortiz
    @baltazarortiz
    ooh yeah I've been wondering if that's possible
    (as in I have been wondering but haven't looked at all because I've been lazy)
    Peter Aaser
    @PeterAaser
    Then I'm barely one step ahead of you
    matrixbot
    @matrixbot
    seldridge I thought GTKWave supported some auxiliary file that could do the mapping (which would be nice if FIRRTL would generate it...).
    Peter Aaser
    @PeterAaser
    Well, the FIRRTL doesn't know that 0b001101 corresponds to some RISC-V opcode
    matrixbot
    @matrixbot
    seldridge There was some effort on Chisel Enums a while back. One aim there was to automatically add annotations to encode what the values actually were. That would then enable something like this (or use of localparam in the emitted Verilog).
    Peter Aaser
    @PeterAaser
    Hmm, probably still useful
    matrixbot
    @matrixbot
    seldridge It's tractable, but you're right---you need to get the semantic information into FIRRTL.
    Baltazar Ortiz
    @baltazarortiz
    definitely would be handy for FSMs and things too
    Peter Aaser
    @PeterAaser
    Yeah
    but for me it suffices to do it manually since it's just tests for a single design, not something general
    Hopefully it's not too bad
    Baltazar Ortiz
    @baltazarortiz
    yea that is definitely a convenience that is not necessary haha
    but yeah for things like opcodes would be actually super time saving
    Peter Aaser
    @PeterAaser
    I bet emacs has this
    huh, for once I'm stumped
    Peter Aaser
    @PeterAaser
    Found it out, it's called a filter file, syntax is just value <tab> name
    Jack Koenig
    @jackkoenig
    The semantic info is actually already being propagated to FIRRTL, we just need to use it to either emit stylized Verilog or data files for various simulators/waveform viewers
    (If you use the experimental ChiselEnum)
    I'm a bit late (I keep closing Gitter accidentally then forgetting to check it), but I would categorize BlueSpec as a big step toward HLS, but by keeping the synthesis aspects within a single cycle, it simplifies the problem a lot
    Jack Koenig
    @jackkoenig
    I really like the approach of guarded atomic actions for expressing certain things (for example, a scheduler), but it can be a really awkward abstraction for other things
    In my idealized world, we'd have guarded atomic actions expressible in Chisel designs so you could use them when you want, but maintain the full expressive generator power
    matrixbot
    @matrixbot
    seldridge There was some work on that a while back at Berkeley, I thought? Maybe a poster at CCC 2018?
    Jack Koenig
    @jackkoenig
    There was some work out of Cambridge I think that did it in Chisel2, and then David Biancolin and Howie Mao at Berkeley also did a prototype (also Chisel2 I think)
    matrixbot
    @matrixbot
    seldridge Just needs a champion, then. I suppose users wanting it would help, too.
    Oron Port
    @soronpo
    You might want to checkout the HDL I'm working on called DFiant. It's an HDL but not an RTL nor an HLS. Kind of a hybrid of dataflow, hardware and software semantics. First release is coming soon.
    Kamyar
    @kammoh
    Boy this all sounds too familiar :)) I also created an atomic action based HDL over then very young Chisel3 as my MSc thesis! Back in 2016!
    I really love BSV and was very excited when they released the code back in January. Though been so busy with my PhD work that haven’t got to quite play with it. I’m also not sure if there’s active development going on around it. A firrtl backend would be a nice start I guess.
    Baltazar Ortiz
    @baltazarortiz
    yea I have a feeling it may be less actively developed re: shift towards general riscv support rather than specific compiler focus as a company
    from what I recall being said at the boston riscv symposium last year
    Kamyar
    @kammoh
    Hope the Chips Alliance people look into some collaboration there
    Seems like a natural push of the markets. I highly doubt they were making much money out of the language/tools really.
    Baltazar Ortiz
    @baltazarortiz
    yeah I think it was MIT and a few academic affiliated defense contractors that were using it afaik
    (and I'm pretty certain MIT wasn't paying for it lol)
    Kamyar
    @kammoh
    I see.
    Baltazar Ortiz
    @baltazarortiz
    (specifically because at least one of the founders is a prof there)
    Kamyar
    @kammoh
    Arvind?
    Baltazar Ortiz
    @baltazarortiz
    yep
    or at least that's my impression from when we interacted for a class years back
    I forget his exact affiliation with it
    Kamyar
    @kammoh
    I love the guy. I so much enjoyed reading their work at the time
    The idea behind action oriented design is pretty smart IMO, and still timely, especially for certain types of designs. And with all the super fast SAT and SMT solvers available today, I guess you can do really neat tricks with it.
    Sorry for hijacking Chisel gitter with this trip down the memory lane lol
    The nostalgia got me too excited I guess
    Jack Koenig
    @jackkoenig
    It's all cool stuff, and thanks for sharing @soronpo, I'll need to take a look at DFiant. I've always seen Chisel as the obvious first step pulling digital design into modern programming languages, but I think there's still a lot of fertile ground to be sowed with new abstractions and paradigms
    For example, Diplomacy conceptually has nothing to do with Chisel, but the need for parameter negotiation kind of falls out of trying to build SoCs and it was just layered on top. You'll notice that Xilinx's IP integrator has a lot in common with Diplomacy
    Jack Koenig
    @jackkoenig
    One of the biggest issues with (existing) HLS and some full languages like BSV is that they make some things really easy while making it really hard if you need to break out of the abstraction. What I like about the generator approach is that there is always that base level with full control. Obviously abstractions built on top can hide things from you and remove some of that control, but at the boundaries of the abstraction you can always do whatever you want in the same language.
    Oron Port
    @soronpo
    So in DFiant you can enjoy both automatic pipelining and hardware generation control. It's not an HLS since control loops must be expressed as FSMs.