Chisel/FIRRTL Discussion and Questions. Use the following template for testing/questions: https://bit.ly/3uZjuHP.
// Instantiate PLL module based on board
val pll: PLL0 = Module(new PLL0(board))
pll.io.clki := clock
// Define if reset should be inverted based on board switch
val customReset = Wire(Bool())
if (invReset) {
customReset := ~reset.asBool()
} else {
customReset := reset
} enc.clock := pll.io.clko
enc.reset := customReset
1 reply
$someThing, (2) 4 hours later there's a post on Twitter showing $someThing working. Was laughing about that with the PWM.
1 reply
An experimental interactive Firrtl simulator based on treadle and wavedrom
1 reply
3 replies
Hello everyone,
we're facing some issues related to SRAM annotations. Currently we are generating blackboxes for SRAM memories inside our modules using the following commands in the Verilog generation App:
object ModuleNameApp extends App
{
val arguments = Array(
"-X", "verilog",
"--repl-seq-mem", "-c:ModuleName:-o:mem.conf",
"--log-level", "info"
)
(new ChiselStage).execute(arguments, Seq(ChiselGeneratorAnnotation(() =>new ModuleName)))
}Our module contains a lot of SyncReadMem objects that should be mapped to SRAMs but we do not want to map them all to SRAM. The above commands will generate blackboxes for all SyncReadMems in the design. Actually we want to annotate certain memories to be SRAMs and others to be mapped into registers even though SyncReadMem object is used. We are not sure how to do that but we are certainly sure that is possible to realize. Apologies if somebody has already asked similar question, but it's not that easy to dig it out.
I'm using the PeekPokeTester from chisel-iotesters. How do I make the test fail unconditionally? I tried using fail, but then I get an output like
[info] [1.462] RAN 10000 CYCLES FAILED FIRST AT CYCLE 10000
...
[info] Run completed in 3 seconds, 466 milliseconds.
[info] Total number of tests run: 1
[info] Suites: completed 1, aborted 0
[info] Tests: succeeded 1, failed 0, canceled 0, ignored 0, pending 0
[info] All tests passed.
[success] Total time: 5 s, completed Jun 8, 2021 8:41:32 PMWhy is it that even after failing, it still passes?
5 replies
ChiselOutputFileAnnotation dumps in the protobuf format if the file extension is ".pb" (I believe), but rocket-chip hides this annotation to pump in its own generated name from the build+config. I'd like to add a DumpProtobufAnnotation to rocket-chip, does this already exist? If I created such a thing would people be interested in having it in the public repo via PR?
2 replies
1 reply
NeuronEvaluator, in Vivado. This version synthesizes to roughly 53 LUTs, while this version synthesizes to roughly 138 LUTs. Apart from some minor code changes, the modules (should) implement the same hardware. Any ideas for potential explanations?
5 replies
Hi guys I am trying to do some quite basic peeking/poking in ChiselTest but cant figure out a way to get it right. I want to enqueue a value to a Decoupled interface and check that an output signal changes in the same cycle
Ex1: Divergent poking/peeking thread
fork {
c.io.input.enqueue(chiselTypeOf(c.io.input).bits.Lit(
_.val -> 1.U
))
}.fork {
c.io.test.expect(true.B)
}.joinEx2: Fails since "enqueue" ends with "joinAndStep", so peek is a cycle late
c.io.input.enqueue(chiselTypeOf(c.io.input).bits.Lit(
_.val -> 1.U
))
c.io.test.expect(true.B)Ex3: Peek happens in the right cycle but is checked before the enqueue happens so its invalid
c.io.test.expect(true.B)
c.io.input.enqueue(chiselTypeOf(c.io.input).bits.Lit(
_.val -> 1.U
))I could of course write my own version of "enqueue" which does not en with joinAndStep but I am a bit confused why the forking version doesnt work
6 replies
make CONFIG=Sha3CPPConfig run-asm-tests, it emits some errors
When I follows the readme in this repo, executing
make CONFIG=Sha3CPPConfig run-asm-tests, it emits some errors
