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    cousteau
    @cousteaulecommandant
    nice!
    Jack Koenig
    @jackkoenig
    if-else is built in to the Scala language so not overloadable, but it's important for conditional instantiation anyway as you mentioned, we would want it regardless
    Bradley Evans
    @bradley-evans
    Good God number datatypes are intensely frustrating in Chisel.
    Bradley Evans
    @bradley-evans
    Do something as an integer, get
    [error]  found   : Int
    [error]  required: chisel3.core.Data
    [error]   stg1_padd := 1 << shiftsize
    Do the same thing as an unsigned integer, get
    [error]   (x: Long)Int <and>
    [error]   (x: Int)Int
    [error]  cannot be applied to (chisel3.core.UInt)
    [error]   stg1_padd := 1 << shiftsize.U
    Schuyler Eldridge
    @seldridge
    I think you're looking for stg1_pad := 1.U << shiftsize
    Bradley Evans
    @bradley-evans
    Haha, well that would make sense.
    Schuyler Eldridge
    @seldridge
    In the first example (which is equivalent to foo := 1), Scala's type checker is erroring because the method := is only defined for Data. In other words, you can only have Data on the right hand side.
    Bradley Evans
    @bradley-evans
    Alright, that's seems clear.
    Schuyler Eldridge
    @seldridge
    The second is similar, but is just saying that you are trying to left shift an integer by something which isn't an integer or a Long (In this case it's some Data, which would be similar to saying 1 << Foo).
    Nice. The type errors can be difficult to parse...
    Bradley Evans
    @bradley-evans
    That's been my # 1 learning curve thus far, honestly
    Richard Xia
    @richardxia
    Does Scala have any mechanism for customizing the type error messages for specific functions? I feel like that would be a big win for all the various DSLs built on top of Scala, and it would be kind of in line with the kinds of "magic" that Scala seems to support like implicits.
    Schuyler Eldridge
    @seldridge
    Not sure @richardxia. I expect there's something... The macro magic you linked is usually the way for doing complicated stuff. The slight danger with that is that deviating heavily from the expected errors produced by the type system may hinder advanced users picking up a library. Once you're in FIRRTL there's more control here as the exceptions are not from the Scala type system and are caught FIRRTL exceptions. There's been a big push to try to make those errors as clean as possible.
    @bradley-evans: If you aren't aware, there's the Scala REPL (read-eval-print-loop) that you can invoke with scala from a console. It's useful for messing around with Scala things (and you can actually invoke a chisel repl with sbt console from the Chisel repository).

    The following is a sketch of what Chisel is doing for connections.

    class Foo { 
      def :=(that: Foo): Unit = println("I connected something!")
    }
    
    val foo = new Foo
    val foo_2 = new Foo
    
    foo := foo_2

    Running this...

    scala> foo := foo_2
    I connected something!
    However, if you try to connect this to an integer, it'll get basically the same error:
    scala> foo := 1
    <console>:10: error: type mismatch;
     found   : Int(1)
     required: Foo
                  foo := 1
    xklqj
    @xklqj
    hei budy , I recognized a problem is that when I try to elaborating a large verilog, it went wrong; I descent the scale it success
    why this happen?
    Ken Zhang
    @kenzhang82
    Hi all, I am new to the chat room, so bear with me if I asked anything silly.
    I am just wondering if Chisel3 can infer dual-port memory (as Firrtl pass to conf file)?
    Maybe this is a question for @seldridge or @jackkoenig?
    Oron Port
    @soronpo
    @richardxia @seldridge look at Scala Clippy https://github.com/softwaremill/scala-clippy
    xklqj
    @xklqj
    image.png
    why it says no fully initial?
    Schuyler Eldridge
    @seldridge
    @xklqj: all signals in a Chisel3 design must be driven by something. Anything
    *Anything not fully initialized will wind up with this error.
    @soronpo: looks neat! Thanks for the pointer.
    Jack Koenig
    @jackkoenig
    @soronpo that's awesome, thanks for showing us that!
    Jack Koenig
    @jackkoenig
    @kenzhang82 I think it only supports single-port, purely a limitation of the implementation: freechipsproject/firrtl#856
    Ken Zhang
    @kenzhang82
    Thanks @jackkoenig! What would be the workaround for dual port memory? Custom transformation?
    Jack Koenig
    @jackkoenig
    Custom transformation or manual instantiation of BlackBox
    Ken Zhang
    @kenzhang82
    Ah ok, I will look into custom transformation, is there any example on this?
    Schuyler Eldridge
    @seldridge
    @kenzhang82: there are some basic examples in chapter 4 of the chisel bootcamp. Also, you can take a look at some of the simpler transforms in FIRRTL. What you're trying to do is close to things in passes/memlib, though that is not a great simple example.
    Ken Zhang
    @kenzhang82
    Thanks @seldridge! I will have a look at this, will definitely come back with questions :-)
    Schuyler Eldridge
    @seldridge
    Sure @kenzhang82. Note: the approach of blackboxing is likely way more straightforward. The custom transform approach is better overall and would benefit the wider community. A PR closing the FIRRTL issue Jack linked (856) would be generally useful.
    Ken Zhang
    @kenzhang82
    Yes agree! I will look into a PR once I got custom transformation working!
    xklqj
    @xklqj
    @seldridge thanks
    image.png
    I write a Vector multiplier, and, it went wrong when Elaborating, where goes wrong?
    Schuyler Eldridge
    @seldridge
    I think
    • you need Input and Output wrappers for your bundle.
    I'm not sure what IDE that is, but the exception you're looking for is one level inside that. I may need to see about unwrapping the options exception to make it more apparent.
    xklqj
    @xklqj
    @seldridge thank you , problem have beee solved!
    xklqj
    @xklqj
    How can I connect two Vector of different length?
    image.png
    xklqj
    @xklqj
    multiplier_array is a hardware to calculate vector multiply, which accept vector of lenth1. whi is a matrix and whi(j) is a vector of lenth2 (lenth2<lenth1), I want to sent whi(j) to multiplier_array.io.vector1, to do a calculate
    Sequencer
    @sequencer
    Is possible to debug the final result of a rocketchip.config.Config?
    since it is designed with partial function, I found no way guess what parameter has been added
    Sequencer
    @sequencer
    is there any iterator for config?