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    Jack Koenig
    @jackkoenig
    Use in assertions
    Kevin Laeufer
    @ekiwi
    Since assertions are synchronous, wouldn't that introduce potential glitches?
    Jack Koenig
    @jackkoenig
    In Chisel, "AsyncReset" means "Async assert, synchronous deassert" so it shouldn't. More importantly though, glitches only happen in hardware and asserts are just for simulation
    Kevin Laeufer
    @ekiwi
    async assert is enough for a glitch
    and assertions could be synthesizable
    Is this only for the use-case where the assertion should be disabled during reset?
    If so, I think this could be fixed by adding an explicit reset to assertions.
    Jack Koenig
    @jackkoenig
    That's fair, but the simulation thing remains
    Kevin Laeufer
    @ekiwi
    In general I would prefer adding resets to more things in firrtl.
    Ideally all side-effecting statements + memory ports should have a reset.
    For my automated coverage work I had to play the reset guessing game a lot.
    Jack Koenig
    @jackkoenig
    How does a reset guessing game work for a memory that semantically isn't reset though?
    Kevin Laeufer
    @ekiwi
    Let's say I want to automatically add an assertion that the address is never out-of-bounds when a write happens. I would like to guard that assertion by the reset scope that the port was instantiated in.
    Another example: Let's say we know the reset signal of the read port. Now we could add an annotation that defines a reset value for the output buffer (which is a feature that seems to be supported on some FPGAs).
    You could argue that the more fundamental solution would be to make reset/clock scopes a concept in firrtl. That seems like it would be too hard to implement though.
    If we add a reset signal to side effecting statements, then it would essentially be able to guard the statement like we already explicitly do in the chisel frontend. With the upside that no cast would be necessary and it would be easier for downstream firrtl passes to know what the reset is.
    Jack Koenig
    @jackkoenig
    clock/reset scopes is one way to do it. I think better is just to have clocks and resets always come in pairs. Sync deassert of async resets is such a key concept in standard physical design flows and you need to know what you're synchronous to
    Kevin Laeufer
    @ekiwi
    Sure. I feel like the simplest way to encode that in the firrtl IR would be to give everything that has a clock signal a reset signal as well.
    Jack Koenig
    @jackkoenig
    yep
    Kevin Laeufer
    @ekiwi
    That would require only small changes and would essentially give you that information (maybe not in the most convenient form).
    Jack Koenig
    @jackkoenig
    Although the main issue with that is that semantically you may not want your memory reset, so I am not sure this really solves your problem
    Kevin Laeufer
    @ekiwi
    Then the next extension to that could be to add clock/reset to bundles.
    Jack Koenig
    @jackkoenig
    I guess you have a reset signal only for verif on mem ports?
    Kevin Laeufer
    @ekiwi
    Yeah
    Or for downstream circuit modifications that require it.
    Like it will just be ignored in the default emission.
    But we can use it if, e.g., we have a scan chain pass that can change the output buffer while it is in reset.
    Or if we want to add assertions.
    Essentially the reset on a memory port does not reset the memory content, it just indicates that in the current cycle the circuit is in reset.
    Jack Koenig
    @jackkoenig
    Yeah, although now I'm going back to the idea of clock/reset domains since you sometimes want similar information for wires
    It's important for verif to know what clock and resets various ports are associated with (for example)
    so sounds like the same issue
    Kevin Laeufer
    @ekiwi
    That is what the second part of my PR is for
    (not done yet...)
    like the first part just tries to extract all reset/clock trees and give them a global name
    the second part is intended to figure out which clock/reset domain each wire is driven by
    like in the end you would have a getClock(signalName) function
    however, this is all complicated by deduplication
    since for example you could have a module that has two clock inputs
    and for some instances, that is the same clock, for others, they are different clocks
    also you could have an input signal that is driven by one clock in one instance and by the other clock in the other instance
    thus if you wanted to add a cover statement for that signal you actually would have to re-duplicate that module
    Muhammad Hadir Khan
    @hadirkhan10
    Hi guys.. after chisel3 this is my next room :D I have cloned the repository and did sbt compile followed by sbt test . However, I am getting 68 Tests Failed..
    1 reply
    Running the tests under the UnitTests.scala with the following command: sbt "testOnly firrtlTests.UnitTests" works fine and passes.
    Muhammad Hadir Khan
    @hadirkhan10
    and I am also noticing that Intellij does not detect the project as an sbt project..
    Muhammad Hadir Khan
    @hadirkhan10
    I have Verilator but not sure about Yosys
    Jack Koenig
    @jackkoenig
    You need Verilator, Yosys, and Z3
    (for FIRRTL, Chisel probably doesn't need Z3)
    Kevin Laeufer
    @ekiwi
    Does anyone know of an easy way to convert a firrtl Reference into a hierarchical path string?
    https://github.com/chipsalliance/treadle/pull/331/files#r644397856
    Kevin Laeufer
    @ekiwi
    Do we have functionality to convert between an AnnotationSeq and a CircuitState?
    Something like:
      private def stateToAnnos(state: firrtl.CircuitState): AnnotationSeq = {
        FirrtlCircuitAnnotation(state.circuit) +: state.annotations
      }
      private def annosToState(annos: AnnotationSeq): firrtl.CircuitState = {
        val circuit = annos.collectFirst { case FirrtlCircuitAnnotation(c) => c }.get
        val filteredAnnos = annos.filterNot(isInternalAnno)
        firrtl.CircuitState(circuit, filteredAnnos)
      }
      private def isInternalAnno(a: Annotation): Boolean = a match {
        case _: FirrtlCircuitAnnotation | _: DesignAnnotation[_] | _:ChiselCircuitAnnotation => true
        case _=> false
      }
    2 replies
    Jack Koenig
    @jackkoenig
    Not that I'm aware of but that would be useful