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    Jack Koenig
    @jackkoenig
    (And for some reason Chisel 3.4.0 always warns about clonetype in Scastie templates, I don't know why)
    Timothy Chong
    @timothychong

    Lol well, I have something very close but am getting a linkage error: https://scastie.scala-lang.org/gdDNgFnJRtOB95nRdUOJCA

    I updated my code to this as well and i got the same error

    Jack Koenig
    @jackkoenig
    See the update, you just need to add scalatest 3.2.2 as a dependency
    The transitive dep is wrong and it's pulling in scalatest 3.0.8, thus the linkage error
    (click Build Settings on the left of a Scastie worksheet to see the SBT stuff)
    Timothy Chong
    @timothychong
    Finally at least got it to run. still seeing that match error. Let met try to fix other deprecations
    thanks
    Jack Koenig
    @jackkoenig
    I think you're hitting a real bug that's probably not fixed by fixing the deprecations (can't be sure though) so if you can get us a .fir maybe we can figure it out
    Like if you run (new ChiselStage).emitVerilog(new MyModule) do you see the same problem?
    Timothy Chong
    @timothychong
    yes I do
    It's really strange. BEcaus eI'm using RRArbiter everywhere, and it's only that one single place that it doesn't work
    Jack Koenig
    @jackkoenig
    Crazy
    Okay try (new ChiselStage).emitChirrtl(new MyModule), that should plop a .fir down in your current working directory
    (If you can share this with us)
    Timothy Chong
    @timothychong
    Can I have email addres to send it to?
    chirrtl finishes succesfully
    Jack Koenig
    @jackkoenig
    jack <dot> koenig 3 <at> gmail (no spaces, replace <symbol>s)
    Andrew Dobis
    @Dobios
    Hi! I'm new to writing FIRRLT transforms and seem to be struggling quite a bit when trying to add ports to a DefModule, since mapping can't really change the size of the Seq[Port] and I can't create a copy of a DefModule since it's abstract. Any ideas as to how one should go about doing this ?
    matrixbot
    @matrixbot
    Schuyler Eldridge Usually you'd want to handle the concrete types of ir.DefModule differently. I.e., match on ir.Module and ir.ExtModule and add ports to either of those. Commonly, you'll be skipping ir.ExtModule.
    matrixbot
    @matrixbot
    Schuyler Eldridge (I was trying to look for a good example of adding ports, but didn't find one.) Both ir.Module and ir.ExtModule are case classes, so they will have a copy method. Roughly, you'd probably be defining a new val portsx = module.ports ++ Seq(...) and then returning module.copy(ports = portsx) for the ir.Module case and the same module for the ir.ExtModule case.
    Andrew Dobis
    @Dobios
    ah ok I see, I'll try differentiating the way I handle the two DefModule types. Thanks!
    3 replies
    matrixbot
    @matrixbot
    Schuyler Eldridge 👍️ Thanks, Kevin Laeufer (Gitter) !
    Sahand Kashani-Akhavan
    @sahandKashani

    Hi. I recall reading this somewhere, but I can't remember where to go recheck. Is assigning a subset of a name illegal in firrtl? Something like this:

    wire x: UInt<4>
    bits(x, 3, 2) <= alpha
    bits(x, 1, 0) <= beta

    You need to instead do something like this instead:

    wire x: UInt<4>
    x <= cat(alpha, beta)

    Is that correct?

    4 replies
    matrixbot
    @matrixbot
    Schuyler Eldridge Yes, you're correct. Put differently, FIRRTL doesn't support subword assignment.
    1 reply
    SJW37
    @SJW37
    Hi. I want to try FIRRTL in the Windows (IntellliJ IDEA) , but there are so many sbt building errors(many files not found). Does anyone use this environment? Or the best choice is Linux? Thanks!
    4 replies
    matrixbot
    @matrixbot
    Schuyler Eldridge Test message. (Supposedly matrix/gitter integration removed @matrixbot. See: https://matrix.org/blog/2020/12/07/gitter-now-speaks-matrix. Trying to see if this works...)
    1 reply
    Jack Koenig
    @jackkoenig
    I can see your test message
    matrixbot
    @matrixbot
    Schuyler Eldridge It's on the roadmap to bridge threads in Gitter to Replies in matrix. The above removal of @martrixbot appears to not be the case or there's something I have to do to update things.
    ekiwi
    @ekiwi:matrix.org
    [m]
    Seems like today in the firrtl meeting the issue of unnamed statements came up again.
    We already talked about this a bit during the summer (wrt. Verification statements) but never reached an agreement on what the syntax for naming statement would be.
    Jack Koenig
    @jackkoenig
    Right, although for Jiuyang's use case, we ended up deciding that a Chisel API to get the current when condition is what he really needs
    But the need for annotating verification statements remains
    ekiwi
    @ekiwi:matrix.org
    [m]
    yeah
    and if we do verification statements, we should also do printf and stop
    Jack Koenig
    @jackkoenig
    yeah
    ekiwi
    @ekiwi:matrix.org
    [m]
    essentially all clocked statements
    Kentox
    @JakubSzczerbinski

    Hi. I'm building a program that converts firrtl to other hardware description language. I currently lower firrtl to LowFirrtl form for an easy translation. I do it like this:

      def lowerFirrtl(circuit : firrtl.ir.Circuit) : firrtl.ir.Circuit = {
        val lowfirrtlC = new LowFirrtlCompiler()
        val lowered = lowfirrtlC.compileAndEmit(CircuitState(circuit, ChirrtlForm)).circuit
        val sinksRemoved = RemoveSinksUsedAsSources.run(lowered) // Running my own Pass
        sinksRemoved
      }

    Translation works fine with LowFirrtl form, but it's not optimal - i need to fine tune which parts of firrtl I lower and what parts i don't. I don't know how to express this with firrtl compiler api.

    1. How can i choose and run a subset of lowering transforms using existing compiler infrastructure?
    2. If I have my own passes (like RemoveSinksUsedAsSources), should i delegate running them to firrtl compiler?
    3. If I should, how do I do it?
    Schuyler Eldridge
    @seldridge
    1. There's new infrastructure for doing this with the FIRRTL 1.3.0 Dependecy API feature which lets you more narrowly run whatever transforms you want, including custom transforms. There's a lot of info about this here: https://gist.github.com/seldridge/0959d714fba6857c5f71ebc7c9044fcf.
    1. Probably. With the latest infrastructure, you can do something like what you're doing with:
      new firrtl.stage.transforms.Compiler(
      targets = Dependency(RemoveSinksUsedAsSources) +: firrtl.stage.Forms.LowFormOptimized
      ).execute(
      CircuitState(foo, Seq.empty)
      )
      This is saying "give me a compiler that will run my RemoveSinksUsedAsSources transform and all the transforms that comprise optimized low form. Usually you see this type of stuff in FIRRTL testing code where you want to run only a specific transform and you just want to satisfy dependencies for it.
    Schuyler Eldridge
    @seldridge
    That firrtl.stage.Forms stuff is defined here. You'll see that these are just sequences of different transforms. So, when you say targets = Seq(Dependency[A], Dependency(B), /** ... */) you're saying "run these things and I don't care how you do it". You may be able to use this directly if you are really just trying to run RemoveSinksUsedAsSources and it has dependencies defined correctly.
    Note: Dependency[A] vs. Dependency(B) where A is a type of some class A that will be constructed on demand and B is an object. This was necessary as transforms may be either classes or transforms, but it's a common confusion when first specifying dependencies.
    Kentox
    @JakubSzczerbinski
    @seldridge This is exactly the information i was looking for. Thank you for help. :)
    Schuyler Eldridge
    @seldridge
    Nice. You're welcome. Here if you have questions.
    Kevin Laeufer
    @ekiwi
    Does anyone have any insight into what it would take to make ConstantPropagation and DeadCodeEliminiation run on any LowForm firrtl?
    I would like to keep all validif that are not trivially invalid/valid.
    Thomas Nijssen
    @nijssen
    Hi all, in the project I'm working on I annotate Statement instances with my own Info classes. This means that I have a bunch of MultiInfos and I was wondering if I'm missing some easy way to traverse these. My current approach is to add an implicit method to statement, foreachInfoRecursive but I was wondering if there's a cleaner way to do this
    11 replies
    Here's my implementation if anyone's curious: https://pastebin.com/pCyT55sG
    Anton Sorokin
    @aasorokighb
    Hi all, Could somebody help me with a problem https://stackoverflow.com/questions/66271752/chisel-3-4-2-syncmem-and-a-black-box-no-memory-replacement-with-repl-seq-mem . If I have a black box module in my code, sync mem is not replaced by an ext reference. To have memories replaced I need either use older Chisel or remove black box.
    5 replies
    Kevin Laeufer
    @ekiwi
    Is there any good way to exclude the chisel3.stage.ChiselCircuitAnnotation from being printed when running the ChiselStage with -ll trace?
    7 replies
    Kamyar Mohajerani
    @kammoh
    What's the canonical way to get a circuit's module hierarchy. All I really need is the hierarchy (instances' names and module) as well as the name and direction of ports for each module.
    6 replies