Where communities thrive


  • Join over 1.5M+ people
  • Join over 100K+ communities
  • Free without limits
  • Create your own community
People
Repo info
Activity
    Muhammad Hadir Khan
    @hadirkhan10
    Hi guys.. after chisel3 this is my next room :D I have cloned the repository and did sbt compile followed by sbt test . However, I am getting 68 Tests Failed..
    1 reply
    Running the tests under the UnitTests.scala with the following command: sbt "testOnly firrtlTests.UnitTests" works fine and passes.
    Muhammad Hadir Khan
    @hadirkhan10
    and I am also noticing that Intellij does not detect the project as an sbt project..
    Muhammad Hadir Khan
    @hadirkhan10
    I have Verilator but not sure about Yosys
    Jack Koenig
    @jackkoenig
    You need Verilator, Yosys, and Z3
    (for FIRRTL, Chisel probably doesn't need Z3)
    Kevin Laeufer
    @ekiwi
    Does anyone know of an easy way to convert a firrtl Reference into a hierarchical path string?
    https://github.com/chipsalliance/treadle/pull/331/files#r644397856
    Kevin Laeufer
    @ekiwi
    Do we have functionality to convert between an AnnotationSeq and a CircuitState?
    Something like:
      private def stateToAnnos(state: firrtl.CircuitState): AnnotationSeq = {
        FirrtlCircuitAnnotation(state.circuit) +: state.annotations
      }
      private def annosToState(annos: AnnotationSeq): firrtl.CircuitState = {
        val circuit = annos.collectFirst { case FirrtlCircuitAnnotation(c) => c }.get
        val filteredAnnos = annos.filterNot(isInternalAnno)
        firrtl.CircuitState(circuit, filteredAnnos)
      }
      private def isInternalAnno(a: Annotation): Boolean = a match {
        case _: FirrtlCircuitAnnotation | _: DesignAnnotation[_] | _:ChiselCircuitAnnotation => true
        case _=> false
      }
    2 replies
    Jack Koenig
    @jackkoenig
    Not that I'm aware of but that would be useful
    Kevin Laeufer
    @ekiwi
    Does firrtl contain a helper function to convert a Target into a "hierarchical name"? Something like mod0.child1.reg?
    2 replies
    BENJAMIN JIN
    @benjamin-jin
    A very simple question. What's the main difference between Pass trait and Transform Trait during Compiler phase? The name Pass seems to mean checking, as it is extended in CheckChirrtl and CInferMDir
    8 replies
    Muhammed Monis
    @monisj
    Hi everyone I have a question regarding optimization in FIRRTL that most transformations regarding circuit design are they all complete because I wanted to automate this transformation issue if they still exist in FIRRTL to resolve and optimize the transforms in the most efficient way possible
    1 reply
    BENJAMIN JIN
    @benjamin-jin
    Hi team, is there any simple method to transform firrtl.ir.Circuit into Seq[IsMember]? I've made my own verwsion, but wanted to check if some sort of APIs already exist. Thx
    12 replies
    Kyle Cho
    @kylecho-semifive
    Hi folks, I am trying to transform 'SyncReset(Bool Reset)' to 'AsyncReset' in my mini-soc by Firrtl transform. Changing reset type, asserts error message while it handles 'Nodes'. Even though reset type changed to Async, still remains firrtl node assuming Sync reset logic, that conflicted with changed one, Async type.
    1 reply
    Wonicon
    @Wonicon
    Hello, I'm new to FIRRTL. How can I print the pass names executed? We have a custom transform inserting verilog format string modifiers that requires running after all checks. It works fine before, but after bumping chisel version along with firrtl version, the outcome of this transform is unexpectedly got checked and inevitably throws BadPrintfException.
    2 replies
    BENJAMIN JIN
    @benjamin-jin
    Hi team, what's the point of using object A extends Phase / Transform / Pass when there is no mutable values described?
    3 replies
    shinezyy
    @shinezyy

    For pull request 2286 (https://github.com/chipsalliance/firrtl/pull/2286/files), for file src/main/scala/firrtl/transforms/DedupAnnotations.scala,

            if (uniqueDedupedAnnos.size == 1 && checkInstanceGraph(target.encapsulatingModule, graph, instancePaths))
              outAnnos += uniqueDedupedAnnos.head
            else
              outAnnos ++= originalAnnos

    originalAnnos might not be 'isLocal'?

    1 reply
    Kevin Laeufer
    @ekiwi
    Does anyone know what the Legalize pass is supposed to do? The scaladoc is definitely out of date:
    // Replace shr by amount >= arg width with 0 for UInts and MSB for SInts
    // TODO replace UInt with zero-width wire instead
    object Legalize extends Pass {
    There seems to be some overlap with PadWidths
    and also ConstantProp
    Kevin Laeufer
    @ekiwi
    So one thing it does is to ensure that the rhs of an assignment is not wider then the lhs.
    Similar to what PadWidths also does.
    Now the question is: for LowFirrtl, do we require the rhs of a connect to be of the same or smaller size than the lhs?
    Essentially what I am asking is: Is this functionality of Legalize necessary to lower Mid into Lo firrtl?
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    This is technically illegal High FIRRTL, but Scala FIRRTL has never enforced this check nor does it remove such connects until Legalize. I would say that this may have been assumed (intentionally or unintentionally) by any transform writer who wrote an inputForm=LowForm transform.
    3 replies
    Jack Koenig
    @jackkoenig
    Legalize would be better named LegalizeForVerilog or perhaps better OptimizationsThatSeemToBeRequiredToBridgeBetweenFIRRTLAndVerilogSemantics (but that one seemed a bit long). The comment should say that though
    I think we should maybe add to the LoFirrtl spec that all connects have the same width on lhs and rhs.
    Jack Koenig
    @jackkoenig
    That sounds like a good idea to me
    lsteveol
    @lsteveol

    I have this problem, you see, some people I work with really like (ok, just about demand) that verilog ports have i_ and o_ prefixes. I was looking at a transform that @ekiwi shared in chipsalliance/chisel3#1059, so I can't claim credit for this (at least the version that worked :)). I was playing around trying to add an onPort method to update the port names, but I keep getting an internal firrtl error. Eventually it has a key not found: in java error. I have not done a lot of FIRRTL transforms so I'm assuming it's mostly me. HEre is a scastie (https://scastie.scala-lang.org/wumZa4vMRVySlfIISMmrLg)

    Based on the debug printing, I'm grabbing the ports and creating a new ir.Port properly. I'm assuming there is some issue when I'm copying the module, but not really sure.

    Kevin Laeufer
    @ekiwi
    If you change the port names of you modules, you also need to change the names at all the places that they are connected to or read.
    That will make your transform a bit harder to write compared to the module name prefixing since module names are only ever used to define instances whereas port names can be used in expressions as well as when connecting to something.
    Jack Koenig
    @jackkoenig
    You'll need to find the SubField for each of those ports on instances of the module and update it; you'll also need to rerun InferTypes (which you can do by invalidating it)
    Kevin Laeufer
    @ekiwi
    You would also have to make sure this runs after LowerTypes since before that you could have multi-directional ports
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    The ManipulateNames transform was supposed to be usable for this type of thing. There's a lot of machinery necessary to do this correctly and to generate the rename map. Without modifying that, you can probably write a pre-pass that will generate rename allow-lists for all input ports, then run ManipulateNames to rename those. Then run it again for output ports with a different allow-list.
    Jack Koenig
    @jackkoenig
    Yeah I think ManipulateNames is your best bet here
    Kevin Laeufer
    @ekiwi
    Do you have an example for that?
    That has examples of doing prefixing/suffixing. The only thing missing is generating allow-list annotations to keep the name changes targeted to just inputs or outputs.
    Kevin Laeufer
    @ekiwi
    Is there ever a reason why a TransformManager would not reschedule a transform after it has been invalidated?
    I currently have a SplitExpression pass that is scheduled as a cleanup by the TransformManager but somehow the manager refuses to move it in front of another transform that is invalidated by SplitExpressoion and is also does not reschedule the invalidated transform.
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    It may not be rescheduled if it's not necessary by something downstream. If it's in the target list, it should always be rescheduled after invalidation.
    Also, the dependency manager ordering is not optimal, but it should be valid. (See: chipsalliance/firrtl#1808)
    lsteveol
    @lsteveol
    Thanks for the reference to ManipulateNames. I'm a little out of my league here and this one looks like a doosy. I will try to see if I can make sense out of it.
    2 replies
    Schuyler Eldridge
    @seldridge:matrix.org
    [m]
    Yep, though you can probably just use an inspecting aspect or whatever just generates annotations. You don't need to actually inject code here (fortunately).
    sam-shahrestani
    @sam-shahrestani
    I'm getting a weird interaction between ForceNameAnnotation and InlineAnnotation. I have 4 modules with InlineAnnotation on them and 4 instances (one for each module) with ForceNameAnnotation on them using the chisel3 util. The Inline works correctly but ForceName ends up renaming the module that wraps these 4 modules, which is very unusual. Am I misunderstanding how this works or do these 2 annotations just not work with each other?
    1 reply
    lsteveol
    @lsteveol

    While I'm pretty sure I already know the answer to this I'm going to ask anyways. Is there a transform that can remove the intermediate assign statements from the Verilog? I have part of a design that is a mix of analog cells. We put this together with Chisel, and later import that back into virtuoso with a schematic import of the verilog. The intermediate assign statements cause a cds_thru cell to be added for each one, which is annoying the layout teams as they now have to add a layout component for this.

    Based on the fact that a <= connect seems to always include this, I don't believe it's possible. I cannot use the Analog attach in this case as most of the ports do have some directionality to them and I place part of the analog cells as a Bundle.

    31 replies
    Kevin Laeufer
    @ekiwi
    Does anyone know if Shell.parse is reentrant?
    4 replies
    anoop
    @mysoreanoop

    Very fundamental newb here;

    I'm able to convert a ~4 MB sized RocketTile's FIR to verilog using this:

    firrtl -i rocket.fir -X verilog -o rocket --log-file logFile -ll info

    But when trying the same for ~102 MB sized BlackParrot's FIR (obtained through Yosys) to verilog using that same command, it doesn't progress, no running logs either unlike that of rocket's run. Anyway to debug further?

    6 replies