For real-time public discussion of FIRRTL. Debates requiring community feedback should be done in firrtl/issues. User questions are welcome.
Lol well, I have something very close but am getting a linkage error: https://scastie.scala-lang.org/gdDNgFnJRtOB95nRdUOJCA
I updated my code to this as well and i got the same error
Build Settings
on the left of a Scastie worksheet to see the SBT stuff)
(new ChiselStage).emitVerilog(new MyModule)
do you see the same problem?
(new ChiselStage).emitChirrtl(new MyModule)
, that should plop a .fir
down in your current working directory
DefModule
, since mapping can't really change the size of the Seq[Port]
and I can't create a copy of a DefModule
since it's abstract. Any ideas as to how one should go about doing this ?
Schuyler Eldridge
(I was trying to look for a good example of adding ports, but didn't find one.) Both ir.Module
and ir.ExtModule
are case classes, so they will have a copy
method. Roughly, you'd probably be defining a new val portsx = module.ports ++ Seq(...)
and then returning module.copy(ports = portsx)
for the ir.Module
case and the same module for the ir.ExtModule
case.
Hi. I recall reading this somewhere, but I can't remember where to go recheck. Is assigning a subset of a name illegal in firrtl? Something like this:
wire x: UInt<4>
bits(x, 3, 2) <= alpha
bits(x, 1, 0) <= beta
You need to instead do something like this instead:
wire x: UInt<4>
x <= cat(alpha, beta)
Is that correct?
Schuyler Eldridge
Test message. (Supposedly matrix/gitter integration removed @matrixbot
. See: https://matrix.org/blog/2020/12/07/gitter-now-speaks-matrix. Trying to see if this works...)
Hi. I'm building a program that converts firrtl to other hardware description language. I currently lower firrtl to LowFirrtl form for an easy translation. I do it like this:
def lowerFirrtl(circuit : firrtl.ir.Circuit) : firrtl.ir.Circuit = {
val lowfirrtlC = new LowFirrtlCompiler()
val lowered = lowfirrtlC.compileAndEmit(CircuitState(circuit, ChirrtlForm)).circuit
val sinksRemoved = RemoveSinksUsedAsSources.run(lowered) // Running my own Pass
sinksRemoved
}
Translation works fine with LowFirrtl form, but it's not optimal - i need to fine tune which parts of firrtl I lower and what parts i don't. I don't know how to express this with firrtl compiler api.
new firrtl.stage.transforms.Compiler(
targets = Dependency(RemoveSinksUsedAsSources) +: firrtl.stage.Forms.LowFormOptimized
).execute(
CircuitState(foo, Seq.empty)
)
This is saying "give me a compiler that will run my RemoveSinksUsedAsSources
transform and all the transforms that comprise optimized low form. Usually you see this type of stuff in FIRRTL testing code where you want to run only a specific transform and you just want to satisfy dependencies for it.firrtl.stage.Forms
stuff is defined here. You'll see that these are just sequences of different transforms. So, when you say targets = Seq(Dependency[A], Dependency(B), /** ... */)
you're saying "run these things and I don't care how you do it". You may be able to use this directly if you are really just trying to run RemoveSinksUsedAsSources
and it has dependencies defined correctly.
Dependency[A]
vs. Dependency(B)
where A
is a type of some class A
that will be constructed on demand and B
is an object. This was necessary as transforms may be either classes or transforms, but it's a common confusion when first specifying dependencies.
validif
that are not trivially invalid/valid.
Statement
instances with my own Info
classes. This means that I have a bunch of MultiInfo
s and I was wondering if I'm missing some easy way to traverse these. My current approach is to add an implicit method to statement, foreachInfoRecursive
but I was wondering if there's a cleaner way to do this