@ndesgranges I can have a look, but a reproducer is always welcome!
@tgingold Oh right I forgot to link the repo where I put the mwe I was talking about :smile:
It's available here : https://github.com/ndesgranges/ghdl_no_wave_mwe
@ndesgranges With this co-simulation, the time is only kept by system-c and not by the vhdl kernel. So the kernel needs some adjustments...
Oh alright, I thought about something like that but I just assumed as a delta is passed to ghdl by systemC, those were synchronized. Now it makes sense
I should have done more investigation first, the lack of support for complex records and array in the VPI is being reported as not being able to find the signal, and I noticed those signals weren't being used in the HDL, so I put 2+2 together and ignored the rest of the equation.
However, I am seeing an issue accessing an architecture-level constant natural that is only used to compute another constant. Perhaps that's an effect of constant folding?
Is there a way to automatically create a black-box entity in work which corresponds to the verilog module?
At this moment you'd have to create a component (stubs) package from a set of the verilog files you want to include. There are some conversion tricks with iverilog, but it gets ugly when generics come into play.