Chisel, SpinalHDL, migen, nmigen, Clash, BlueSpec, Silice, myhdl, TL-Verilog... all those are domain specific languages, most of them focused on a very specific topic (writting RISCV microarchitectures).
@fatsiefs:matrix.org I don't mean they are necessarily designed to be domain specific in the long term, but I meant they are mostly used as such.
- Chisel was originally single-clock-domain and could not handle async descriptions. I think that multiple clock domains are supported since v3? Not sure about async.
- SpinalHDL is mostly used for composing SoCs, mainly around the very successful VexRiscv, Murax, Briey, etc. The language itself can be used for "any" design, and people are writing peripherals for the RISC-V SoCs using those. However, I didn't see any project using SpinalHDL for hardware not part of a RISC-V SoC.
- Migen (and Litex) are very used for composing SoCs too. It's possible to write hardware with them, but most of the designs I see do integrate HDL cores and use those for building the SoC.
AFAIK, those generate Verilog. SpinalHDL can generate VHDL too, but it's not the default in most of the available designs, hence tweaks are required.
nmigen, I acknowledge it's probably the most different from all of these. whitequark has a very interesting understanding of technology and that's a breakthrough. In this case, the problem I see is the ecosystem. While other languages can explicitly interact with traditional vendor tools, nmigen has been very tightly coupled to Yosys and CXXRTL. Together with the almost absolute lack of documentation, that made it not appealing to people needing an stable solution for the next decades. From a VHDL user perspective, I cannot use nmigen together with VHDL designs and have them simulated without converting the VHDL to something else.
However, if any of these languages might seriously replace VHDL or Verilog in the future, I think nmigen might be the strongest candidate. Moreover, whitequark acknowledged that nmigen and CXXRTL share concepts with VHDL (maybe more than with Verilog, 'cause maybe nmigen is fixing the problems with the Verilog language which do not exist in VHDL because they were solved years/decades ago). From this point of view, I would love nmigen to become "VHDL with Python syntax", not a Python HDL, but THE Python VHDL.
Anyway, my claim is that none of these projects is a valid candidate for the industry in less than 5-10 years of development. All of those languages are 5-10 years old, and now is when we can start talking about them as serious solutions. I was not criticising bluntly, I was just stating that hardware development is hard, very regardless of how clever you are or the languages you use. System Verilog or VHDL are not "better" per se, they just have been worked on for 6x longer.
I would rather nmigen not be VHDL with a python syntax as I prefer the implementation of clock domain and synchronous logic over the VHDL one. Maybe you are more interested in MyHDL then as I see that as a reimplementation of VHDL/Verilog mistakes in python 🙂
I disagree on the 5-10 year timeframe for nmigen usability. I have used VHDL code in nmigen design, used cocotb with modelsim (proprietary I know) for mixed-signal sim. But I agree this is own development not general available.
@fatsiefs:matrix.org I meant 5-10y since someone decides to (re)invent a language, not from now onward. nmigen has been 3y in development after 10y of migen and +10y of myHDL. It didn't come out of nowhere.
By the same token, 3y ago cocotb was dead, after a very successful start. FOSSi, Kaleb and others spent the last 2 years working so hard, and they still have at least 1y of development for starting to consider it mature.
Note that my reply was targeted at a person that suggested he would write his own HDL from scratch. I suggested him to better build on any of those existing projects/languages precisely so those can get to maturity faster.
You would compare nMigen to VHDL? I think they pretty different in approach. nMigen is a Python metaprogramming framework on top of a functional RTL-oriented DSL. VHDL is a more traditional simulation language.
@ktbarret, could you please elaborate? I'm thinking about a user who needs to learn both hardware design and a language for hardware description at the same time, as a tool for them to use in the following 1-2 decades. I don't think whether the implementation is a metaprogramming language or a traditional language is relevant. It's about what they can express and what they cannot. Entities/architectures/modules/components/bodies, structs/records/interfaces, FFs/memories, boolean logic/muxes, fixed-point and floating-point DSP...
there are mature FP toolboxes for MyHDL I know of. But isn't this a bit off topic?
@hackfin, would mind providing any reference?
We can continue in hdl/community, if you prefer.
Ive been thinking of the board that the MisTER project uses, which is a DE-10 Nano (intel). How is the ecosystem with that vs the xilinx based stuff of the basys3
@vblanco20-1 I suggest you ask in the symbiflow channel in IRC, and/or in project mistral. Support for intel/altera devices is less advanced than Lattice or Xilinx. For Xilinx, there are two PnR tools, nextpnr and VTR. For Intel, I think they are working with nextpnr only.
I would recommend an ECP5 device and a board with an Artix.
I would stay away from Zynq, unless you have any actual usage for the single or dual ARM cores. You cannot use the PL without understanding and initialising the PS.
I have a PYNQ-Z1 and some Arty, and there is no advantage in the first one for RTL only designs. However, Zynq is very interesting if you want to run Linux on ARM and accelerate things in the FPGA.
the de10nano is used in the mister project which is something i could contribute to or have fun tinkering with
I believe that the mister project might greatly benefit from being ported/adapted to an open board based on one of the largest ECP5. However, mister seems to be not only the FPGA board, but a whole stack of boards...
the main thing is on the de-10 nano, but the extras are to give it extra ram, more usb ports, and analog output (VGA)
@vblanco20-1 With some ECP5 or Artix boards you would have some of those extras. For instance https://shop.lambdaconcept.com/home/46-2-ecpix-5.html#/2-ecpix_5_fpga-ecpix_5_85f, as direct alternative to Arty/Zybo.
@umarcor
and they still have at least 1y of development for starting to consider it mature.
Probably a lot more than that, especially with how few contributors we have, how averse to large changes the project is, and how grindy the review process is. To meet some of the needs of users we need to do significant rewrites of many of the components, but I don't see that as possible... And there is a lot of related work that needs to be done:
- integrate with other project management tools like VUnit and/or edalize/fusesoc
- develop a verification framework on top of cocotb
- write articles, case studies, develop more serious examples, tutorial videos, etc.
At the current pace I see it as 4 more years.
I don't think whether the implementation is a metaprogramming language or a traditional language is relevant.
Sure. I didn't know to what extent you were trying to make comparisons.
I suggested him to better build on any of those existing projects/languages precisely so those can get to maturity faster.
This is kind of what I am doing as a verification framework on top of cocotb. It keeps changing and it's looking more and more like an HDL... Processes, "modules" (probably need a better name since Python already has modules), channels and synchronous channels (blocking send returns after placement in queue vs recv by destination, which a generalization of a "signal"), accompanied by a set of HDL datatypes making their way into cocotb.
@ktbarrett, thanks so much for acknowledging that. I believe that VUnit, OSVVM and others are in a similar state. Even though their codebase is more mature (OSVVM +20y, VUnit almost 10y), the integration with others, writing articles, tutorials, etc. is a challenge we all need to address, because we are very few in each of the projects.
This is kind of what I am doing as a verification framework on top of cocotb. It keeps changing and it's looking more and more like an HDL... (...) accompanied by a set of HDL datatypes making their way into cocotb.
I don't know if I already told you about my conception of using cocotb's Python interface for driving the VHDL Verification Components of VUnit and/or OSVVM. Not something I will solve in the following weeks or months, but that is my target in say 5 years. Hence, there is lots of conceptual overlapping with what you are trying to achieve. Channels, message passing, queues, a virtual memory with permissions, etc. all those software tools for verification are already written in VHDL and customised for the standard interfaces. We should not reimplement that in Python nor do bit-banging through indirect cosimulation interfaces. Unfortunately, I'm not expert enough yet for proposing an specific implementation for achieving that. First things first, I need to solve the envvar management in VUnit, which that cocotb user asked, and which I'm finding I need for other use cases (customising LD_LIBRARY_PATH when doing cosimulation with VUnit and GHDL through VHPIDIRECT).
I know this is probably irrelevant for most of you, professional users of VHDL/GHDL, but I do believe it is very important with regard to articles, case studies, examples, tutorials, etc.
- If a subprogram has a foreign attribute, the foreign body must exist. This was discussed in ghdl/ghdl#793 and we all agree that's something the tools might require.
- A subprogram needs to have a VHDL body, even if a foreign attribute is declared. This is something we all agree not to make sense, and which might be an oversight. However, we could not find where in the LRM is that specified, nor did I find any issue in the ghdl repo where we discussed it explicitly. I know we have discussed it either there or in this chat, tho. Can you or anyone provide a hint?
all those software tools for verification are already written in VHDL and customised for the standard interfaces. We should not reimplement that in Python nor do bit-banging through indirect cosimulation interfaces.
Well, this is kind of the entire point of cocotb. Write testbenches in Python instead of VHDL or (System)Verilog. I could see implementing drivers/monitors in VHDL or SystemVerilog and controlling them from a cocotb test as a (very) useful optimization and to cover cases where the VPI isn't sufficient (tri-state drivers), but that would require a lot of tooling because I would like something like that to be automated. One of the things people like about cocotb is not having to write any VHDL/(System)Verilog for the testbench, or even write a top at all. And I don't see how that precludes implementing the same functionality in cocotb to handle the cases where moving the implementation to HDL is not possible or just too time consuming to be useful.
You might be interested in pybfms which is similar to this. IIRC it uses VPI system tasks to enable communication between cocotb and Verilog BFMs.
I'm not familiar enough with cocotb+verilator or cocotb+iverilog yet
That reminds me of one more task to reach maturity: Mature the GHDL and Verilator VPI/VHPI interfaces so cocotb will work with them.
but that would require a lot of tooling because I would like something like that to be automated.
A verification component is a black-box with a software API on one side and a hardware interface on the other. Adding an VC between the HDL interface and the software procedure is the most automated and transparent solution for the users. They should not write any code in any case, just their application specific software procedure. The question is whether VCs need to be written in HDL only, in Python only, or half HDL half Python. I believe it needs to be the last one. We can request developers to know both languages, even though users won't. Currently, developers need to know VPI/VHPI although users do not.
I agree it would require tooling, but not more than it required to automate the usage of HDL only VCs or Python only VCs. That is a library management issue we have in the EDA industry, not specific in this case.
You might be interested in pybfms which is similar to this. IIRC it uses VPI system tasks to enable communication between cocotb and Verilog BFMs.
Yeah, that's kind of the idea. Anyway, we first need to solve how to call VHDL subprograms from a foreign language, which is not defined yet. That's part of the VHDPI discussion, but it might not get into the first revision.
In ghdl-cosim there is an example of the opposite: using a VHDL protected type with foreign attributes for exposing a C API in VHDL. The idea is the same: get a handle of the class/object from the other language and call the methods as the software API of the "standard interface".
Mature the GHDL and Verilator VPI/VHPI interfaces so cocotb will work with them.
This is my priority with GHDL. I need to get to implement some changes myself so I can actually start fixing things and not just annoying Tristan with bug reports and requests.
In the last days, I did a lot of enhancements for pyVHDLModel which is used by pyVHDLParser and also GHDL. The VHDL language model is the basis for the dom namespace in pyGHDL.
I think until end of the week I can finalize a first pretty-printing demonstrator, which parses a VHDL file with GHDL's libghdl, uses GHDL's Python bindings and transforms GHDL's internal data structure (IIR) to a Python-based document object model (DOM) that represents a VHDL file with instances of classes and references (points) among them.
The pretty-printer example emits the translated object model to text. From there it should be easy to provide other output formats like JSON or YAML (if needed).
Of cause, users can use the object model in there own libraries or tools based on GHDL's Python API.
Even if my own project pyVHDLParser is not as advanced and working like GHDL, it's till planned to have a second source besides parsing via libghdl to create a object model using pyVHDLModel as a common interface.
What is it good for?
We can now think about generating documentation - especially in Python based tools like Sphinx - from VHDL code parsed by libghdl. What I can do so far is:
- list entities, architectures, packages, package bodies, contexts and configurations
- list generics (constants) for entities
- list ports (signals) for entities
- list declared items in architectures (packages will follow soon)
- constants
- signals
- types
- subtypes
- functions (procedures will follow soon)
- list constraints in e.g. port/generic declarations
- parse expressions in e.g. range expressions like
std_logic_vector(BITS - 1 downto 0)
Example output (pretty printed DOM):
Document 'testsuite\pyunit\SimpleEntity.vhdl':
Entities:
- entity1
Generics:
- bits : in positive
Ports:
- clock : in std_logic
- reset : in std_logic
- q : out std_logic_vector(bits - 1 downto 0)
Architectures:
- behav
Packages:
PackageBodies:
Configurations:
Contexts:cli/DOM.py which can be called with a VHDL file as parameter to call the pretty-printing example code.