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tgingold commented #1387

xiretza

@xiretza_gitlab

you can only specify generics for the top-level entity on the command line, but that's the same in sim as in synth

T. Meissner

@tmeissner

Ah, okay. When I think about it, it makes sense. Sorry for the confusion ;)

tgingold

@tgingold

@tmeissner You can also analyze the source files and then do the synthesis using: ghdl --std=08 -gGENERIC=val -e design

@ndesgranges I can have a look, but a reproducer is always welcome!

tgingold

@tgingold

@ndesgranges With this co-simulation, the time is only kept by system-c and not by the vhdl kernel. So the kernel needs some adjustments...

Nicolas Desgranges

@ndesgranges

@ndesgranges I can have a look, but a reproducer is always welcome!

@tgingold Oh right I forgot to link the repo where I put the mwe I was talking about :smile:
It's available here : https://github.com/ndesgranges/ghdl_no_wave_mwe

@ndesgranges With this co-simulation, the time is only kept by system-c and not by the vhdl kernel. So the kernel needs some adjustments...

Oh alright, I thought about something like that but I just assumed as a delta is passed to ghdl by systemC, those were synchronized. Now it makes sense

tgingold

@tgingold

Delta cycles are correctly handled, but not the time.

Kaleb Barrett

@ktbarrett

@tgingold Is there way to turn off certain optimizations? A lot of the unit tests in cocotb fail because GHDL is seemingly optimizing away signals that don't contribute to outputs.

tgingold

@tgingold

No, signals are never removed. Maybe they aren't visible by VPI because they are complex records ?

Kaleb Barrett

@ktbarrett

I should have done more investigation first, the lack of support for complex records and array in the VPI is being reported as not being able to find the signal, and I noticed those signals weren't being used in the HDL, so I put 2+2 together and ignored the rest of the equation.

However, I am seeing an issue accessing an architecture-level constant natural that is only used to compute another constant. Perhaps that's an effect of constant folding?

Kaleb Barrett

@ktbarrett

here

Florian Klink

@flokli

indeed I did :-)

GlenNicholls

@GlenNicholls

@anhangaba I figured out the problem from :point_up: June 3, 2020 12:21 PM: ghdl/ghdl#1382

tgingold

@tgingold

@ktbarrett Even in case of constant folding, the constants should remain accessible. I will have a look, but please open an issue so that I don't forget.

Kamyar Mohajerani

@kammoh

I understand that mixed VHDL/Verilog is not officially supported with ghdl-yosys-plugin but does anyone know of any tricks/workarounds to make top-level VHDL with verilog submodules work in Yosys?

tgingold

@tgingold

The current trick is to first synthesize the verilog submodules and then the vhdl top-level.

If you use generics/parameters, that's harder...

Martin

@hackfin

@kammoh I'm just in process of putting together some examples as jupyter NBs, will take a bit though. Will post the repo here these days.

Kamyar Mohajerani

@kammoh

@tgingold this is exactly what I was doing. I just found out what the problem was: entity instantiation of a verilog module does not work, but component instantiation seems to be working. Is that a know limitation?

xiretza

@xiretza_gitlab

that's to be expected, a verilog module isn't represented as an entity in your work library

Kamyar Mohajerani

@kammoh

@xiretza_gitlab you are absolutely right. The bummer is that this seems to be working in non-open-source mixed-hdl tools

Is there a way to automatically create a black-box entity in work which corresponds to the verilog module?

Kamyar Mohajerani

@kammoh

@tgingold would there be any way to access VHDL-defined constants inside the verilog submodules?

Martin

@hackfin

Is there a way to automatically create a black-box entity in work which corresponds to the verilog module?

At this moment you'd have to create a component (stubs) package from a set of the verilog files you want to include. There are some conversion tricks with iverilog, but it gets ugly when generics come into play.

Martin

@hackfin

I pushed a preliminary 'playground' here: https://github.com/hackfin/hdlplayground containing some notebooks with examples (hit Binder button, wait until it's up, use play button to step through the cells to reproduce)

Haven't gotten round yet to document the Verilog blackbox inferences in detail, I'm afraid

Kamyar Mohajerani

@kammoh

Thanks @hackfin! That looks very interesting!

tgingold

@tgingold

@kammoh Yes, you have to use components.

Kamyar Mohajerani

@kammoh

Got it! Thanks!

Lars Asplund

@LarsAsplund

Yesterday I setup a VUnit + GHDL CI for IBM's newly open sourced core. After a few modifications it compiles locally on my machine (mcode) but not in the CI (LLVM). Any ideas? https://github.com/LarsAsplund/a2i/runs/824196581?check_suite_focus=true#step:4:307

Patrick Lehmann

@Paebbels

The SoftCPU mentioned by @LarsAsplund is this: https://github.com/openpower-cores/a2i - The core was used by IBM in the BlueGene super computers.

T. Meissner

@tmeissner

Cool project. Reminds me of the opensparc thing years ago. Sadly, the RTL consists mostly of instantiations of a lot of primitive components. Not so good to learning & understanding the behavior of the system

But for that purposes we have microwatt 🙂

Patrick Lehmann

@Paebbels

this code is works also on FPGAs and I saw some Vivado scripts inside

Patrick Lehmann

@Paebbels

ReadTheDocs has now traffic analytics for the GHDL documentation:

And here per page:

Oh, and we get a list of searched word:

GlenNicholls

@GlenNicholls

@Paebbels that is interesting! For the total # of views, is there a way to sort that by different users?

Patrick Lehmann

@Paebbels

what I show here, is everything we get for now

the graph seams to start on 15.06.2020. I compare GHDl and other projects of me, all have the same date

GlenNicholls

@GlenNicholls

That is nice! It would be really interesting to see how search queries by a specific user relate to different searches they make for documentation purposes.

tgingold

@tgingold

@LarsAsplund Did you publish your changes ?

Lars Asplund

@LarsAsplund

@tgingold All my changes are on my own fork. I want to make it green before making a PR. Is that what you mean?

Lars Asplund

@LarsAsplund

@tgingold Do you want me to open an issue and try to create a smaller reproducable example or do you already know what the problem is?

tgingold

@tgingold

No, I don't know what the problems are. If you have reproducers, that would be helpful!

Lars Asplund

@LarsAsplund

@tgingold I don't have any reproducers but Iet's see what I can find

I have an idea